xref: /linux/Documentation/devicetree/bindings/clock/qcom,milos-dispcc.yaml (revision 8d2b0853add1d7534dc0794e3c8e0b9e8c4ec640) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,milos-dispcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display Clock & Reset Controller on Milos
8
9maintainers:
10  - Luca Weiss <luca.weiss@fairphone.com>
11
12description: |
13  Qualcomm display clock control module provides the clocks, resets and power
14  domains on Milos.
15
16  See also: include/dt-bindings/clock/qcom,milos-dispcc.h
17
18properties:
19  compatible:
20    const: qcom,milos-dispcc
21
22  clocks:
23    items:
24      - description: Board XO source
25      - description: Sleep clock source
26      - description: Display's AHB clock
27      - description: GPLL0 source from GCC
28      - description: Byte clock from DSI PHY0
29      - description: Pixel clock from DSI PHY0
30      - description: Link clock from DP PHY0
31      - description: VCO DIV clock from DP PHY0
32
33required:
34  - compatible
35  - clocks
36  - '#power-domain-cells'
37
38allOf:
39  - $ref: qcom,gcc.yaml#
40
41unevaluatedProperties: false
42
43examples:
44  - |
45    #include <dt-bindings/clock/qcom,milos-gcc.h>
46    #include <dt-bindings/phy/phy-qcom-qmp.h>
47    clock-controller@af00000 {
48        compatible = "qcom,milos-dispcc";
49        reg = <0x0af00000 0x20000>;
50        clocks = <&bi_tcxo_div2>,
51                 <&sleep_clk>,
52                 <&gcc GCC_DISP_AHB_CLK>,
53                 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
54                 <&mdss_dsi0_phy 0>,
55                 <&mdss_dsi0_phy 1>,
56                 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
57                 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
58        #clock-cells = <1>;
59        #reset-cells = <1>;
60        #power-domain-cells = <1>;
61    };
62
63...
64