xref: /linux/Documentation/devicetree/bindings/clock/qcom,ipq9650-gcc.yaml (revision 0eaed89c18aeedf0898baf2dbf5ff027c6795152)

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,ipq9650-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on IPQ9650

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on IPQ9650

  See also:
    include/dt-bindings/clock/qcom,ipq9650-gcc.h
    include/dt-bindings/reset/qcom,ipq9650-gcc.h

properties:
  compatible:
    const: qcom,ipq9650-gcc

  clocks:
    items:
      - description: Board XO source
      - description: Sleep clock source
      - description: PCIE30 PHY0 pipe clock source
      - description: PCIE30 PHY1 pipe clock source
      - description: PCIE30 PHY2 pipe clock source
      - description: PCIE30 PHY3 pipe clock source
      - description: PCIE30 PHY4 pipe clock source
      - description: USB PCIE wrapper pipe clock source
      - description: NSS common clock source

  '#power-domain-cells': false

  '#interconnect-cells':
    const: 1

required:
  - compatible
  - clocks

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    clock-controller@1800000 {
      compatible = "qcom,ipq9650-gcc";
      reg = <0x01800000 0x40000>;
      clocks = <&xo_board_clk>,
               <&sleep_clk>,
               <&pcie30_phy0_pipe_clk>,
               <&pcie30_phy1_pipe_clk>,
               <&pcie30_phy2_pipe_clk>,
               <&pcie30_phy3_pipe_clk>,
               <&pcie30_phy4_pipe_clk>,
               <&usb3phy_0_cc_pipe_clk>,
               <&nss_cmn_clk>;
      #clock-cells = <1>;
      #reset-cells = <1>;
    };
...