1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/qcom,ipq9650-gcc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Global Clock & Reset Controller on IPQ9650 8 9maintainers: 10 - Bjorn Andersson <andersson@kernel.org> 11 - Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> 12 13description: | 14 Qualcomm global clock control module provides the clocks, resets and power 15 domains on IPQ9650 16 17 See also: 18 include/dt-bindings/clock/qcom,ipq9650-gcc.h 19 include/dt-bindings/reset/qcom,ipq9650-gcc.h 20 21properties: 22 compatible: 23 const: qcom,ipq9650-gcc 24 25 clocks: 26 items: 27 - description: Board XO source 28 - description: Sleep clock source 29 - description: PCIE30 PHY0 pipe clock source 30 - description: PCIE30 PHY1 pipe clock source 31 - description: PCIE30 PHY2 pipe clock source 32 - description: PCIE30 PHY3 pipe clock source 33 - description: PCIE30 PHY4 pipe clock source 34 - description: USB PCIE wrapper pipe clock source 35 - description: NSS common clock source 36 37 '#power-domain-cells': false 38 39 '#interconnect-cells': 40 const: 1 41 42required: 43 - compatible 44 - clocks 45 46allOf: 47 - $ref: qcom,gcc.yaml# 48 49unevaluatedProperties: false 50 51examples: 52 - | 53 clock-controller@1800000 { 54 compatible = "qcom,ipq9650-gcc"; 55 reg = <0x01800000 0x40000>; 56 clocks = <&xo_board_clk>, 57 <&sleep_clk>, 58 <&pcie30_phy0_pipe_clk>, 59 <&pcie30_phy1_pipe_clk>, 60 <&pcie30_phy2_pipe_clk>, 61 <&pcie30_phy3_pipe_clk>, 62 <&pcie30_phy4_pipe_clk>, 63 <&usb3phy_0_cc_pipe_clk>, 64 <&nss_cmn_clk>; 65 #clock-cells = <1>; 66 #reset-cells = <1>; 67 }; 68... 69