1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/qcom,x1e80100-camcc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Camera Clock & Reset Controller on x1e80100 8 9maintainers: 10 - Bryan O'Donoghue <bryan.odonoghue@linaro.org> 11 12description: | 13 Qualcomm camera clock control module provides the clocks, resets and power 14 domains on x1e80100. 15 16 See also: 17 include/dt-bindings/clock/qcom,x1e80100-camcc.h 18 19allOf: 20 - $ref: qcom,gcc.yaml# 21 22properties: 23 compatible: 24 enum: 25 - qcom,x1e80100-camcc 26 27 reg: 28 maxItems: 1 29 30 clocks: 31 items: 32 - description: Camera AHB clock from GCC 33 - description: Board XO source 34 - description: Board active XO source 35 - description: Sleep clock source 36 37 power-domains: 38 items: 39 - description: A phandle to the MXC power-domain 40 - description: A phandle to the MMCX power-domain 41 42 required-opps: 43 maxItems: 1 44 description: 45 A phandle to an OPP node describing MMCX performance points. 46 47required: 48 - compatible 49 - clocks 50 - power-domains 51 - required-opps 52 53unevaluatedProperties: false 54 55examples: 56 - | 57 #include <dt-bindings/clock/qcom,x1e80100-gcc.h> 58 #include <dt-bindings/clock/qcom,rpmh.h> 59 #include <dt-bindings/power/qcom,rpmhpd.h> 60 clock-controller@ade0000 { 61 compatible = "qcom,x1e80100-camcc"; 62 reg = <0xade0000 0x20000>; 63 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 64 <&rpmhcc RPMH_CXO_CLK>, 65 <&rpmhcc RPMH_CXO_CLK_A>, 66 <&sleep_clk>; 67 power-domains = <&rpmhpd RPMHPD_MXC>, 68 <&rpmhpd RPMHPD_MMCX>; 69 required-opps = <&rpmhpd_opp_low_svs>; 70 #clock-cells = <1>; 71 #reset-cells = <1>; 72 #power-domain-cells = <1>; 73 }; 74... 75