xref: /linux/Documentation/devicetree/bindings/clock/qcom,shikra-gcc.yaml (revision cbe8aadf1551f3f4a853f24b3b96d9f0eea49c53) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,shikra-gcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Global Clock & Reset Controller on Qualcomm Shikra SoC
8
9maintainers:
10  - Imran Shaik <imran.shaik@oss.qualcomm.com>
11  - Taniya Das <taniya.das@oss.qualcomm.com>
12
13description: |
14  Global clock control module provides the clocks, resets and power
15  domains on Qualcomm Shikra SoC platform.
16
17  See also: include/dt-bindings/clock/qcom,shikra-gcc.h
18
19properties:
20  compatible:
21    const: qcom,shikra-gcc
22
23  clocks:
24    items:
25      - description: Board XO source
26      - description: Sleep clock source
27      - description: EMAC0 sgmiiphy mac rclk source
28      - description: EMAC0 sgmiiphy mac tclk source
29      - description: EMAC1 sgmiiphy mac rclk source
30      - description: EMAC1 sgmiiphy mac tclk source
31      - description: PCIE Pipe clock source
32      - description: USB3 phy wrapper pipe clock source
33
34  power-domains:
35    items:
36      - description: CX domain
37
38required:
39  - compatible
40  - clocks
41  - power-domains
42  - '#power-domain-cells'
43
44allOf:
45  - $ref: qcom,gcc.yaml#
46
47unevaluatedProperties: false
48
49examples:
50  - |
51    #include <dt-bindings/clock/qcom,rpmcc.h>
52    #include <dt-bindings/power/qcom-rpmpd.h>
53    clock-controller@1400000 {
54        compatible = "qcom,shikra-gcc";
55        reg = <0x01400000 0x1f0000>;
56        clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
57                 <&sleep_clk>,
58                 <&emac0_sgmiiphy_rclk>,
59                 <&emac0_sgmiiphy_tclk>,
60                 <&emac1_sgmiiphy_rclk>,
61                 <&emac1_sgmiiphy_tclk>,
62                 <&pcie_pipe_clk>,
63                 <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
64        power-domains = <&rpmpd RPMPD_VDDCX>;
65        #clock-cells = <1>;
66        #power-domain-cells = <1>;
67        #reset-cells = <1>;
68    };
69
70...
71