xref: /linux/Documentation/devicetree/bindings/clock/qcom,nord-negcc.yaml (revision 0fc8f6200d2313278fbf4539bbab74677c685531) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,nord-negcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global North East Clock & Reset Controller on Nord SoC
8
9maintainers:
10  - Taniya Das <taniya.das@oss.qualcomm.com>
11
12description: |
13  Qualcomm global clock control (NE) module provides the clocks, resets
14  and power domains on Nord SoC.
15
16  See also: include/dt-bindings/clock/qcom,nord-negcc.h
17
18properties:
19  compatible:
20    const: qcom,nord-negcc
21
22  clocks:
23    items:
24      - description: Board XO source
25      - description: Sleep clock source
26      - description: UFS Phy Rx symbol 0 clock source
27      - description: UFS Phy Rx symbol 1 clock source
28      - description: UFS Phy Tx symbol 0 clock source
29      - description: USB3 Phy sec wrapper pipe clock source
30      - description: USB3 Phy wrapper pipe clock source
31
32required:
33  - compatible
34  - clocks
35  - '#power-domain-cells'
36
37allOf:
38  - $ref: qcom,gcc.yaml#
39
40unevaluatedProperties: false
41
42examples:
43  - |
44    #include <dt-bindings/clock/qcom,rpmh.h>
45    clock-controller@8900000 {
46      compatible = "qcom,nord-negcc";
47      reg = <0x08900000 0xf4200>;
48      clocks = <&rpmhcc RPMH_CXO_CLK>,
49               <&sleep_clk>,
50               <&ufs_phy_rx_symbol_0_clk>,
51               <&ufs_phy_rx_symbol_1_clk>,
52               <&ufs_phy_tx_symbol_0_clk>,
53               <&usb3_phy_sec_pipe_clk>,
54               <&usb3_phy_pipe_clk>;
55      #clock-cells = <1>;
56      #reset-cells = <1>;
57      #power-domain-cells = <1>;
58    };
59
60...
61