xref: /linux/Documentation/devicetree/bindings/clock/qcom,ipq5210-gcc.yaml (revision e65f4718a577fcc84d40431f022985898b6dbf2e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,ipq5210-gcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller on IPQ5210
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
12
13description: |
14  Qualcomm global clock control module provides the clocks, resets and power
15  domains on IPQ5210
16
17  See also:
18    include/dt-bindings/clock/qcom,ipq5210-gcc.h
19    include/dt-bindings/reset/qcom,ipq5210-gcc.h
20
21properties:
22  compatible:
23    const: qcom,ipq5210-gcc
24
25  clocks:
26    items:
27      - description: Board XO source
28      - description: Sleep clock source
29      - description: PCIE30 PHY0 pipe clock source
30      - description: PCIE30 PHY1 pipe clock source
31      - description: USB3 PHY pipe clock source
32      - description: NSS common clock source
33
34  '#power-domain-cells': false
35
36  '#interconnect-cells':
37    const: 1
38
39required:
40  - compatible
41  - clocks
42
43allOf:
44  - $ref: qcom,gcc.yaml#
45
46unevaluatedProperties: false
47
48examples:
49  - |
50    clock-controller@1800000 {
51      compatible = "qcom,ipq5210-gcc";
52      reg = <0x01800000 0x40000>;
53      clocks = <&xo_board_clk>,
54               <&sleep_clk>,
55               <&pcie30_phy0_pipe_clk>,
56               <&pcie30_phy1_pipe_clk>,
57               <&usb3phy_0_cc_pipe_clk>,
58               <&nss_cmn_clk>;
59      #clock-cells = <1>;
60      #reset-cells = <1>;
61    };
62...
63