xref: /linux/Documentation/devicetree/bindings/clock/qcom,hawi-gcc.yaml (revision 2ed2e359dea752e7758d29a423033031a0b96584) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,hawi-gcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller on Hawi
8
9maintainers:
10  - Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com>
11
12description: |
13  Qualcomm global clock control module provides the clocks, resets and power
14  domains on Hawi.
15
16  See also: include/dt-bindings/clock/qcom,hawi-gcc.h
17
18properties:
19  compatible:
20    const: qcom,hawi-gcc
21
22  clocks:
23    items:
24      - description: Board XO source
25      - description: Board Always On XO source
26      - description: Sleep clock source
27      - description: PCIE 0 Pipe clock source
28      - description: PCIE 1 Pipe clock source
29      - description: UFS PHY RX symbol 0 clock
30      - description: UFS PHY RX symbol 1 clock
31      - description: UFS PHY TX symbol 0 clock
32      - description: USB3 PHY wrapper pipe clock
33
34required:
35  - compatible
36  - clocks
37  - '#power-domain-cells'
38
39allOf:
40  - $ref: qcom,gcc.yaml#
41
42unevaluatedProperties: false
43
44examples:
45  - |
46    #include <dt-bindings/clock/qcom,rpmh.h>
47    clock-controller@100000 {
48      compatible = "qcom,hawi-gcc";
49      reg = <0x00100000 0x1f4200>;
50      clocks = <&rpmhcc RPMH_CXO_CLK>,
51               <&rpmhcc RPMH_CXO_CLK_A>,
52               <&sleep_clk>,
53               <&pcie0_phy>,
54               <&pcie1_phy>,
55               <&ufs_mem_phy 0>,
56               <&ufs_mem_phy 1>,
57               <&ufs_mem_phy 2>,
58               <&usb_1_qmpphy>;
59      #clock-cells = <1>;
60      #reset-cells = <1>;
61      #power-domain-cells = <1>;
62    };
63...
64