xref: /linux/Documentation/devicetree/bindings/clock/qcom,eliza-dispcc.yaml (revision 0fc8f6200d2313278fbf4539bbab74677c685531) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,eliza-dispcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Display Clock & Reset Controller for Qualcomm Eliza SoC
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Konrad Dybcio <konradybcio@kernel.org>
12  - Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
13
14description: |
15  Display clock control module provides the clocks, resets and power
16  domains on Qualcomm Eliza SoC platform.
17
18  See also:
19  - include/dt-bindings/clock/qcom,eliza-dispcc.h
20
21properties:
22  compatible:
23    enum:
24      - qcom,eliza-dispcc
25
26  clocks:
27    items:
28      - description: Board XO source
29      - description: Board Always On XO source
30      - description: Display's AHB clock
31      - description: sleep clock
32      - description: Byte clock from DSI PHY0
33      - description: Pixel clock from DSI PHY0
34      - description: Byte clock from DSI PHY1
35      - description: Pixel clock from DSI PHY1
36      - description: Link clock from DP PHY0
37      - description: VCO DIV clock from DP PHY0
38      - description: Link clock from DP PHY1
39      - description: VCO DIV clock from DP PHY1
40      - description: Link clock from DP PHY2
41      - description: VCO DIV clock from DP PHY2
42      - description: Link clock from DP PHY3
43      - description: VCO DIV clock from DP PHY3
44      - description: HDMI link clock from HDMI PHY
45
46  power-domains:
47    maxItems: 1
48
49  required-opps:
50    maxItems: 1
51
52required:
53  - compatible
54  - clocks
55  - '#power-domain-cells'
56
57allOf:
58  - $ref: qcom,gcc.yaml#
59
60unevaluatedProperties: false
61
62examples:
63  - |
64    #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
65    #include <dt-bindings/clock/qcom,eliza-gcc.h>
66    #include <dt-bindings/clock/qcom,rpmh.h>
67    #include <dt-bindings/power/qcom,rpmhpd.h>
68    clock-controller@af00000 {
69        compatible = "qcom,eliza-dispcc";
70        reg = <0x0af00000 0x20000>;
71        clocks = <&bi_tcxo_div2>,
72                 <&bi_tcxo_ao_div2>,
73                 <&gcc GCC_DISP_AHB_CLK>,
74                 <&sleep_clk>,
75                 <&dsi0_phy DSI_BYTE_PLL_CLK>,
76                 <&dsi0_phy DSI_PIXEL_PLL_CLK>,
77                 <&dsi1_phy DSI_BYTE_PLL_CLK>,
78                 <&dsi1_phy DSI_PIXEL_PLL_CLK>,
79                 <&dp0_phy 0>,
80                 <&dp0_phy 1>,
81                 <&dp1_phy 0>,
82                 <&dp1_phy 1>,
83                 <&dp2_phy 0>,
84                 <&dp2_phy 1>,
85                 <&dp3_phy 0>,
86                 <&dp3_phy 1>,
87                 <&hdmi_phy>;
88
89        #clock-cells = <1>;
90        #power-domain-cells = <1>;
91        #reset-cells = <1>;
92
93        power-domains = <&rpmhpd RPMHPD_MMCX>;
94        required-opps = <&rpmhpd_opp_low_svs>;
95    };
96...
97