xref: /linux/Documentation/devicetree/bindings/clock/qca,ath79-pll.yaml (revision 8d2b0853add1d7534dc0794e3c8e0b9e8c4ec640) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qca,ath79-pll.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Atheros ATH79 PLL controller
8
9maintainers:
10  - Alban Bedel <albeu@free.fr>
11  - Antony Pavlov <antonynpavlov@gmail.com>
12
13description: >
14  The PLL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
15
16properties:
17  compatible:
18    oneOf:
19      - items:
20          - const: qca,ar9132-pll
21          - const: qca,ar9130-pll
22      - items:
23          - enum:
24              - qca,ar7100-pll
25              - qca,ar7240-pll
26              - qca,ar9130-pll
27              - qca,ar9330-pll
28              - qca,ar9340-pll
29              - qca,qca9530-pll
30              - qca,qca9550-pll
31              - qca,qca9560-pll
32
33  reg:
34    maxItems: 1
35
36  clock-names:
37    items:
38      - const: ref
39
40  clocks:
41    maxItems: 1
42
43  '#clock-cells':
44    const: 1
45
46  clock-output-names:
47    items:
48      - const: cpu
49      - const: ddr
50      - const: ahb
51
52required:
53  - compatible
54  - reg
55  - clock-names
56  - clocks
57  - '#clock-cells'
58
59additionalProperties: false
60
61examples:
62  - |
63    clock-controller@18050000 {
64        compatible = "qca,ar9132-pll", "qca,ar9130-pll";
65        reg = <0x18050000 0x20>;
66        clock-names = "ref";
67        clocks = <&extosc>;
68        #clock-cells = <1>;
69        clock-output-names = "cpu", "ddr", "ahb";
70    };
71