1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/nxp,lpc1850-cgu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NXP LPC1850 Clock Generation Unit (CGU) 8 9description: > 10 The CGU generates multiple independent clocks for the core and the 11 peripheral blocks of the LPC18xx. Each independent clock is called 12 a base clock and itself is one of the inputs to the two Clock 13 Control Units (CCUs) which control the branch clocks to the 14 individual peripherals. 15 16 The CGU selects the inputs to the clock generators from multiple 17 clock sources, controls the clock generation, and routes the outputs 18 of the clock generators through the clock source bus to the output 19 stages. Each output stage provides an independent clock source and 20 corresponds to one of the base clocks for the LPC18xx. 21 22 Above text taken from NXP LPC1850 User Manual. 23 24maintainers: 25 - Frank Li <Frank.Li@nxp.com> 26 27properties: 28 compatible: 29 const: nxp,lpc1850-cgu 30 31 reg: 32 maxItems: 1 33 34 '#clock-cells': 35 const: 1 36 description: | 37 Which base clocks that are available on the CGU depends on the 38 specific LPC part. Base clocks are numbered from 0 to 27. 39 40 Number: Name: Description: 41 0 BASE_SAFE_CLK Base safe clock (always on) for WWDT 42 1 BASE_USB0_CLK Base clock for USB0 43 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsystem, 44 SPI, and SGPIO 45 3 BASE_USB1_CLK Base clock for USB1 46 4 BASE_CPU_CLK System base clock for ARM Cortex-M core 47 and APB peripheral blocks #0 and #2 48 5 BASE_SPIFI_CLK Base clock for SPIFI 49 6 BASE_SPI_CLK Base clock for SPI 50 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Receive clock 51 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Transmit clock 52 9 BASE_APB1_CLK Base clock for APB peripheral block # 1 53 10 BASE_APB3_CLK Base clock for APB peripheral block # 3 54 11 BASE_LCD_CLK Base clock for LCD 55 12 BASE_ADCHS_CLK Base clock for ADCHS 56 13 BASE_SDIO_CLK Base clock for SD/MMC 57 14 BASE_SSP0_CLK Base clock for SSP0 58 15 BASE_SSP1_CLK Base clock for SSP1 59 16 BASE_UART0_CLK Base clock for UART0 60 17 BASE_UART1_CLK Base clock for UART1 61 18 BASE_UART2_CLK Base clock for UART2 62 19 BASE_UART3_CLK Base clock for UART3 63 20 BASE_OUT_CLK Base clock for CLKOUT pin 64 24-21 - Reserved 65 25 BASE_AUDIO_CLK Base clock for audio system (I2S) 66 26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock output 67 27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock output 68 69 BASE_PERIPH_CLK and BASE_SPI_CLK is only available on LPC43xx. 70 BASE_ADCHS_CLK is only available on LPC4370. 71 72 clocks: 73 maxItems: 5 74 75 clock-indices: 76 minItems: 1 77 maxItems: 28 78 79 clock-output-names: 80 minItems: 1 81 maxItems: 28 82 83required: 84 - compatible 85 - reg 86 - clocks 87 - '#clock-cells' 88 89additionalProperties: false 90 91examples: 92 - | 93 clock-controller@40050000 { 94 compatible = "nxp,lpc1850-cgu"; 95 reg = <0x40050000 0x1000>; 96 #clock-cells = <1>; 97 clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; 98 }; 99 100