1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/nvidia,tegra124-dfll.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NVIDIA Tegra124 (and later) DFLL FCPU clocksource 8 9maintainers: 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 13description: 14 The DFLL IP block on Tegra is a root clocksource designed for clocking 15 the fast CPU cluster. It consists of a free-running voltage controlled 16 oscillator connected to the CPU voltage rail (VDD_CPU), and a closed 17 loop control module that will automatically adjust the VDD_CPU voltage 18 by communicating with an off-chip PMIC either via an I2C bus or via 19 PWM signals. 20 21properties: 22 compatible: 23 enum: 24 - nvidia,tegra124-dfll 25 - nvidia,tegra210-dfll 26 27 reg: 28 items: 29 - description: DFLL control logic 30 - description: I2C output logic 31 - description: Integrated I2C controller 32 - description: Look-up table RAM for voltage register values 33 34 interrupts: 35 maxItems: 1 36 37 "#clock-cells": 38 const: 0 39 40 clocks: 41 items: 42 - description: Clock source for the DFLL control logic 43 - description: Closed loop reference clock 44 - description: Clock source for the integrated I2C controller 45 46 clock-names: 47 items: 48 - const: soc 49 - const: ref 50 - const: i2c 51 52 clock-output-names: 53 description: Name of the clock output 54 items: 55 - const: dfllCPU_out 56 57 resets: 58 minItems: 1 59 maxItems: 2 60 61 reset-names: 62 minItems: 1 63 items: 64 - const: dvco 65 - const: dfll 66 67 vdd-cpu-supply: 68 description: Regulator for the CPU voltage rail that the DFLL 69 hardware will start controlling. The regulator will be queried for 70 the I2C register, control values and supported voltages. 71 72 nvidia,sample-rate: 73 description: Sample rate of the DFLL control loop 74 $ref: /schemas/types.yaml#/definitions/uint32 75 minimum: 12500 76 maximum: 25000 77 78 nvidia,droop-ctrl: 79 description: Droop control parameter (CL_DVFS_DROOP_CTRL) in the TRM 80 $ref: /schemas/types.yaml#/definitions/uint32 81 82 nvidia,force-mode: 83 description: See the field DFLL_PARAMS_FORCE_MODE in the TRM 84 $ref: /schemas/types.yaml#/definitions/uint32 85 oneOf: 86 - description: disabled 87 const: 0 88 - description: fixed delay mode 89 const: 1 90 - description: auto mode 91 const: 2 92 93 nvidia,cf: 94 description: Numeric value, see the field DFLL_PARAMS_CF_PARAM in the TRM 95 $ref: /schemas/types.yaml#/definitions/uint32 96 minimum: 0 97 maximum: 63 98 99 nvidia,ci: 100 description: Numeric value, see the field DFLL_PARAMS_CI_PARAM in the TRM 101 $ref: /schemas/types.yaml#/definitions/uint32 102 minimum: 0 103 maximum: 7 104 105 nvidia,cg: 106 description: Numeric value, see the field DFLL_PARAMS_CG_PARAM in the TRM 107 $ref: /schemas/types.yaml#/definitions/uint32 108 minimum: 0 109 maximum: 255 110 111 # optional properties 112 nvidia,cg-scale: 113 description: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM 114 $ref: /schemas/types.yaml#/definitions/flag 115 116 nvidia,pwm-to-pmic: 117 description: Use PWM to control regulator rather than I2C 118 $ref: /schemas/types.yaml#/definitions/flag 119 120 nvidia,i2c-fs-rate: 121 description: I2C transfer rate, if using full speed mode 122 $ref: /schemas/types.yaml#/definitions/uint32 123 enum: [100000, 400000] 124 125 # required properties for PWM mode 126 nvidia,pwm-period-nanoseconds: 127 description: Period of PWM square wave in nanoseconds 128 $ref: /schemas/types.yaml#/definitions/uint32 129 minimum: 1000 130 maximum: 1000000000 131 132 nvidia,pwm-tristate-microvolts: 133 description: Regulator voltage in microvolts when PWM control is disabled 134 and the PWM output is tristated. Note that this voltage is configured in 135 hardware, typically via a resistor divider. 136 $ref: /schemas/types.yaml#/definitions/uint32 137 minimum: 0 138 maximum: 3300000 139 140 nvidia,pwm-min-microvolts: 141 description: Regulator voltage in microvolts when PWM control is enabled 142 and PWM output is low. Hence, this is the minimum output voltage that 143 the regulator supports when PWM control is enabled. 144 $ref: /schemas/types.yaml#/definitions/uint32 145 minimum: 0 146 maximum: 3300000 147 148 nvidia,pwm-voltage-step-microvolts: 149 description: | 150 Voltage increase in micro volts corresponding to a 1/33th increase 151 in duty cycle. For example, the voltage for 2/33th duty cycle would be: 152 153 nvidia,pwm-min-microvolts + nvidia,pwm-voltage-step-microvolts * 2 154 $ref: /schemas/types.yaml#/definitions/uint32 155 minimum: 0 156 maximum: 100000 157 158 pinctrl-0: 159 description: I/O pad configuration when PWM control is enabled 160 161 pinctrl-1: 162 description: I/O pad configuration when PWM control is disabled 163 164 pinctrl-names: 165 items: 166 - const: dvfs_pwm_enable 167 - const: dvfs_pwm_disable 168 169required: 170 - compatible 171 - reg 172 - interrupts 173 - "#clock-cells" 174 - clocks 175 - clock-names 176 - clock-output-names 177 - resets 178 - reset-names 179 - nvidia,sample-rate 180 - nvidia,droop-ctrl 181 - nvidia,force-mode 182 - nvidia,cf 183 - nvidia,ci 184 - nvidia,cg 185 186additionalProperties: false 187 188allOf: 189 - if: 190 properties: 191 compatible: 192 contains: 193 const: nvidia,tegra124-dfll 194 then: 195 properties: 196 resets: 197 maxItems: 1 198 199 reset-names: 200 maxItems: 1 201 else: 202 properties: 203 resets: 204 minItems: 2 205 206 reset-names: 207 minItems: 2 208 209 - if: 210 required: 211 - nvidia,pwm-to-pmic 212 then: 213 required: 214 - nvidia,pwm-min-microvolts 215 - nvidia,pwm-period-nanoseconds 216 - nvidia,pwm-tristate-microvolts 217 - nvidia,pwm-voltage-step-microvolts 218 else: 219 required: 220 - vdd-cpu-supply 221 222examples: 223 - | 224 #include <dt-bindings/clock/tegra124-car.h> 225 #include <dt-bindings/interrupt-controller/arm-gic.h> 226 #include <dt-bindings/reset/tegra124-car.h> 227 228 clock@70110000 { 229 compatible = "nvidia,tegra124-dfll"; 230 reg = <0x70110000 0x100>, /* DFLL control */ 231 <0x70110000 0x100>, /* I2C output control */ 232 <0x70110100 0x100>, /* Integrated I2C controller */ 233 <0x70110200 0x100>; /* Look-up table RAM */ 234 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 235 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>, 236 <&tegra_car TEGRA124_CLK_DFLL_REF>, 237 <&tegra_car TEGRA124_CLK_I2C5>; 238 clock-names = "soc", "ref", "i2c"; 239 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; 240 reset-names = "dvco"; 241 #clock-cells = <0>; 242 clock-output-names = "dfllCPU_out"; 243 vdd-cpu-supply = <&vdd_cpu>; 244 245 nvidia,sample-rate = <12500>; 246 nvidia,droop-ctrl = <0x00000f00>; 247 nvidia,force-mode = <1>; 248 nvidia,cf = <10>; 249 nvidia,ci = <0>; 250 nvidia,cg = <2>; 251 252 nvidia,i2c-fs-rate = <400000>; 253 }; 254 255 - | 256 #include <dt-bindings/clock/tegra210-car.h> 257 #include <dt-bindings/interrupt-controller/arm-gic.h> 258 #include <dt-bindings/reset/tegra210-car.h> 259 260 clock@70110000 { 261 compatible = "nvidia,tegra210-dfll"; 262 reg = <0x70110000 0x100>, /* DFLL control */ 263 <0x70110000 0x100>, /* I2C output control */ 264 <0x70110100 0x100>, /* Integrated I2C controller */ 265 <0x70110200 0x100>; /* Look-up table RAM */ 266 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 268 <&tegra_car TEGRA210_CLK_DFLL_REF>, 269 <&tegra_car TEGRA210_CLK_I2C5>; 270 clock-names = "soc", "ref", "i2c"; 271 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>, 272 <&tegra_car 155>; 273 reset-names = "dvco", "dfll"; 274 #clock-cells = <0>; 275 clock-output-names = "dfllCPU_out"; 276 vdd-cpu-supply = <&vdd_cpu>; 277 278 nvidia,sample-rate = <25000>; 279 nvidia,droop-ctrl = <0x00000f00>; 280 nvidia,force-mode = <1>; 281 nvidia,cf = <6>; 282 nvidia,ci = <0>; 283 nvidia,cg = <2>; 284 285 nvidia,pwm-min-microvolts = <708000>; /* 708mV */ 286 nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */ 287 nvidia,pwm-to-pmic; 288 nvidia,pwm-tristate-microvolts = <1000000>; 289 nvidia,pwm-voltage-step-microvolts = <19200>; /* 19.2mV */ 290 }; 291