1*f2cb67d7SRob Herring (Arm)# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*f2cb67d7SRob Herring (Arm)%YAML 1.2 3*f2cb67d7SRob Herring (Arm)--- 4*f2cb67d7SRob Herring (Arm)$id: http://devicetree.org/schemas/clock/moxa,moxart-clock.yaml# 5*f2cb67d7SRob Herring (Arm)$schema: http://devicetree.org/meta-schemas/core.yaml# 6*f2cb67d7SRob Herring (Arm) 7*f2cb67d7SRob Herring (Arm)title: MOXA ART Clock Controllers 8*f2cb67d7SRob Herring (Arm) 9*f2cb67d7SRob Herring (Arm)maintainers: 10*f2cb67d7SRob Herring (Arm) - Krzysztof Kozlowski <krzk@kernel.org> 11*f2cb67d7SRob Herring (Arm) 12*f2cb67d7SRob Herring (Arm)description: 13*f2cb67d7SRob Herring (Arm) MOXA ART SoCs allow to determine PLL output and APB frequencies by reading 14*f2cb67d7SRob Herring (Arm) registers holding multiplier and divisor information. 15*f2cb67d7SRob Herring (Arm) 16*f2cb67d7SRob Herring (Arm)properties: 17*f2cb67d7SRob Herring (Arm) compatible: 18*f2cb67d7SRob Herring (Arm) enum: 19*f2cb67d7SRob Herring (Arm) - moxa,moxart-apb-clock 20*f2cb67d7SRob Herring (Arm) - moxa,moxart-pll-clock 21*f2cb67d7SRob Herring (Arm) 22*f2cb67d7SRob Herring (Arm) "#clock-cells": 23*f2cb67d7SRob Herring (Arm) const: 0 24*f2cb67d7SRob Herring (Arm) 25*f2cb67d7SRob Herring (Arm) reg: 26*f2cb67d7SRob Herring (Arm) maxItems: 1 27*f2cb67d7SRob Herring (Arm) 28*f2cb67d7SRob Herring (Arm) clocks: 29*f2cb67d7SRob Herring (Arm) maxItems: 1 30*f2cb67d7SRob Herring (Arm) 31*f2cb67d7SRob Herring (Arm) clock-output-names: true 32*f2cb67d7SRob Herring (Arm) 33*f2cb67d7SRob Herring (Arm)additionalProperties: false 34*f2cb67d7SRob Herring (Arm) 35*f2cb67d7SRob Herring (Arm)required: 36*f2cb67d7SRob Herring (Arm) - compatible 37*f2cb67d7SRob Herring (Arm) - "#clock-cells" 38*f2cb67d7SRob Herring (Arm) - reg 39