xref: /linux/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml (revision 502d45774af09f1c681c754c4b7cdfb5d7f72fd9) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4
5$id: http://devicetree.org/schemas/clock/mediatek,mt8173-mfgtop.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: MediaTek MT8173 MFG TOP controller
9
10maintainers:
11  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
12
13description:
14  The MFG TOP glue layer controls various signals going to the MFG (GPU)
15  block on the MT8173.
16
17properties:
18  compatible:
19    const: mediatek,mt8173-mfgtop
20
21  reg:
22    maxItems: 1
23
24  clocks:
25    maxItems: 4
26
27  clock-names:
28    items:
29      - const: sys
30      - const: mem
31      - const: core
32      - const: clk26m
33
34  power-domains:
35    maxItems: 1
36
37  '#clock-cells':
38    const: 1
39
40  '#power-domain-cells':
41    const: 0
42
43required:
44  - compatible
45  - reg
46  - clocks
47  - clock-names
48  - power-domains
49  - '#clock-cells'
50  - '#power-domain-cells'
51
52additionalProperties: false
53
54examples:
55  - |
56        #include <dt-bindings/clock/mt8173-clk.h>
57        #include <dt-bindings/power/mt8173-power.h>
58
59        clock-controller@13fff000 {
60            compatible = "mediatek,mt8173-mfgtop";
61            reg = <0x13fff000 0x1000>;
62            clocks = <&topckgen CLK_TOP_AXI_MFG_IN_SEL>,
63                     <&topckgen CLK_TOP_MEM_MFG_IN_SEL>,
64                     <&topckgen CLK_TOP_MFG_SEL>,
65                     <&clk26m>;
66            clock-names = "sys", "mem", "core", "clk26m";
67            power-domains = <&spm MT8173_POWER_DOMAIN_MFG>;
68            #clock-cells = <1>;
69            #power-domain-cells = <0>;
70        };
71