xref: /linux/Documentation/devicetree/bindings/clock/maxim,max9485.yaml (revision 8d2b0853add1d7534dc0794e3c8e0b9e8c4ec640) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/maxim,max9485.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Maxim MAX9485 Programmable Audio Clock Generator
8
9maintainers:
10  - Daniel Mack <daniel@zonque.org>
11
12description: >
13  Maxim MAX9485 Programmable Audio Clock Generator exposes 4 clocks in total:
14
15    - MAX9485_MCLKOUT:  A gated, buffered output of the input clock of 27 MHz
16    - MAX9485_CLKOUT:   A PLL that can be configured to 16 different discrete
17                        frequencies
18    - MAX9485_CLKOUT[1,2]:  Two gated outputs for MAX9485_CLKOUT
19
20  MAX9485_CLKOUT[1,2] are children of MAX9485_CLKOUT which upchain all rate set
21  requests.
22
23properties:
24  compatible:
25    const: maxim,max9485
26
27  reg:
28    maxItems: 1
29
30  clocks:
31    description: Input clock. Must provide 27 MHz
32    maxItems: 1
33
34  clock-names:
35    items:
36      - const: xclk
37
38  '#clock-cells':
39    const: 1
40
41  reset-gpios:
42    description: >
43      GPIO descriptor connected to the #RESET input pin
44
45  vdd-supply:
46    description: A regulator node for Vdd
47
48  clock-output-names:
49    description: Name of output clocks, as defined in common clock bindings
50    items:
51      - const: mclkout
52      - const: clkout
53      - const: clkout1
54      - const: clkout2
55
56required:
57  - compatible
58  - reg
59  - clocks
60  - clock-names
61  - '#clock-cells'
62
63additionalProperties: false
64
65examples:
66  - |
67    #include <dt-bindings/gpio/gpio.h>
68
69    i2c {
70        #address-cells = <1>;
71        #size-cells = <0>;
72
73        clock-controller@63 {
74            compatible = "maxim,max9485";
75            reg = <0x63>;
76            #clock-cells = <1>;
77            clock-names = "xclk";
78            clocks = <&xo_27mhz>;
79            reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
80            vdd-supply = <&reg_3v3>;
81        };
82    };
83