1*45a8d350SRob Herring (Arm)# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*45a8d350SRob Herring (Arm)%YAML 1.2 3*45a8d350SRob Herring (Arm)--- 4*45a8d350SRob Herring (Arm)$id: http://devicetree.org/schemas/clock/marvell,cp110-clock.yaml# 5*45a8d350SRob Herring (Arm)$schema: http://devicetree.org/meta-schemas/core.yaml# 6*45a8d350SRob Herring (Arm) 7*45a8d350SRob Herring (Arm)title: Marvell Armada CP110 System Controller Clocks 8*45a8d350SRob Herring (Arm) 9*45a8d350SRob Herring (Arm)maintainers: 10*45a8d350SRob Herring (Arm) - Gregory Clement <gregory.clement@bootlin.com> 11*45a8d350SRob Herring (Arm) - Miquel Raynal <miquel.raynal@bootlin.com> 12*45a8d350SRob Herring (Arm) 13*45a8d350SRob Herring (Arm)description: > 14*45a8d350SRob Herring (Arm) The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K/931x 15*45a8d350SRob Herring (Arm) SoCs. It contains system controllers, which provide several registers giving 16*45a8d350SRob Herring (Arm) access to numerous features: clocks, pin-muxing and many other SoC 17*45a8d350SRob Herring (Arm) configuration items. 18*45a8d350SRob Herring (Arm) 19*45a8d350SRob Herring (Arm)properties: 20*45a8d350SRob Herring (Arm) compatible: 21*45a8d350SRob Herring (Arm) const: marvell,cp110-clock 22*45a8d350SRob Herring (Arm) 23*45a8d350SRob Herring (Arm) "#clock-cells": 24*45a8d350SRob Herring (Arm) const: 2 25*45a8d350SRob Herring (Arm) description: > 26*45a8d350SRob Herring (Arm) The first cell must be 0 or 1. 0 for the core clocks and 1 for the 27*45a8d350SRob Herring (Arm) gateable clocks. The second cell identifies the particular core clock or 28*45a8d350SRob Herring (Arm) gateable clocks. 29*45a8d350SRob Herring (Arm) 30*45a8d350SRob Herring (Arm) The following clocks are available: 31*45a8d350SRob Herring (Arm) 32*45a8d350SRob Herring (Arm) - Core clocks 33*45a8d350SRob Herring (Arm) - 0 0 APLL 34*45a8d350SRob Herring (Arm) - 0 1 PPv2 core 35*45a8d350SRob Herring (Arm) - 0 2 EIP 36*45a8d350SRob Herring (Arm) - 0 3 Core 37*45a8d350SRob Herring (Arm) - 0 4 NAND core 38*45a8d350SRob Herring (Arm) - 0 5 SDIO core 39*45a8d350SRob Herring (Arm) 40*45a8d350SRob Herring (Arm) - Gateable clocks 41*45a8d350SRob Herring (Arm) - 1 0 Audio 42*45a8d350SRob Herring (Arm) - 1 1 Comm Unit 43*45a8d350SRob Herring (Arm) - 1 2 NAND 44*45a8d350SRob Herring (Arm) - 1 3 PPv2 45*45a8d350SRob Herring (Arm) - 1 4 SDIO 46*45a8d350SRob Herring (Arm) - 1 5 MG Domain 47*45a8d350SRob Herring (Arm) - 1 6 MG Core 48*45a8d350SRob Herring (Arm) - 1 7 XOR1 49*45a8d350SRob Herring (Arm) - 1 8 XOR0 50*45a8d350SRob Herring (Arm) - 1 9 GOP DP 51*45a8d350SRob Herring (Arm) - 1 11 PCIe x1 0 52*45a8d350SRob Herring (Arm) - 1 12 PCIe x1 1 53*45a8d350SRob Herring (Arm) - 1 13 PCIe x4 54*45a8d350SRob Herring (Arm) - 1 14 PCIe / XOR 55*45a8d350SRob Herring (Arm) - 1 15 SATA 56*45a8d350SRob Herring (Arm) - 1 16 SATA USB 57*45a8d350SRob Herring (Arm) - 1 17 Main 58*45a8d350SRob Herring (Arm) - 1 18 SD/MMC/GOP 59*45a8d350SRob Herring (Arm) - 1 21 Slow IO (SPI, NOR, BootROM, I2C, UART) 60*45a8d350SRob Herring (Arm) - 1 22 USB3H0 61*45a8d350SRob Herring (Arm) - 1 23 USB3H1 62*45a8d350SRob Herring (Arm) - 1 24 USB3 Device 63*45a8d350SRob Herring (Arm) - 1 25 EIP150 64*45a8d350SRob Herring (Arm) - 1 26 EIP197 65*45a8d350SRob Herring (Arm) 66*45a8d350SRob Herring (Arm)required: 67*45a8d350SRob Herring (Arm) - compatible 68*45a8d350SRob Herring (Arm) - "#clock-cells" 69*45a8d350SRob Herring (Arm) 70*45a8d350SRob Herring (Arm)additionalProperties: false 71