1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/marvell,cp110-clock.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Marvell Armada CP110 System Controller Clocks 8 9maintainers: 10 - Gregory Clement <gregory.clement@bootlin.com> 11 - Miquel Raynal <miquel.raynal@bootlin.com> 12 13description: > 14 The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K/931x 15 SoCs. It contains system controllers, which provide several registers giving 16 access to numerous features: clocks, pin-muxing and many other SoC 17 configuration items. 18 19properties: 20 compatible: 21 const: marvell,cp110-clock 22 23 "#clock-cells": 24 const: 2 25 description: > 26 The first cell must be 0 or 1. 0 for the core clocks and 1 for the 27 gateable clocks. The second cell identifies the particular core clock or 28 gateable clocks. 29 30 The following clocks are available: 31 32 - Core clocks 33 - 0 0 APLL 34 - 0 1 PPv2 core 35 - 0 2 EIP 36 - 0 3 Core 37 - 0 4 NAND core 38 - 0 5 SDIO core 39 40 - Gateable clocks 41 - 1 0 Audio 42 - 1 1 Comm Unit 43 - 1 2 NAND 44 - 1 3 PPv2 45 - 1 4 SDIO 46 - 1 5 MG Domain 47 - 1 6 MG Core 48 - 1 7 XOR1 49 - 1 8 XOR0 50 - 1 9 GOP DP 51 - 1 11 PCIe x1 0 52 - 1 12 PCIe x1 1 53 - 1 13 PCIe x4 54 - 1 14 PCIe / XOR 55 - 1 15 SATA 56 - 1 16 SATA USB 57 - 1 17 Main 58 - 1 18 SD/MMC/GOP 59 - 1 21 Slow IO (SPI, NOR, BootROM, I2C, UART) 60 - 1 22 USB3H0 61 - 1 23 USB3H1 62 - 1 24 USB3 Device 63 - 1 25 EIP150 64 - 1 26 EIP197 65 66required: 67 - compatible 68 - "#clock-cells" 69 70additionalProperties: false 71