1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/marvell,dove-divider-clock.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Marvell Dove PLL Divider Clock 8 9maintainers: 10 - Andrew Lunn <andrew@lunn.ch> 11 - Gregory Clement <gregory.clement@bootlin.com> 12 13description: > 14 Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide 15 high speed clocks for a number of peripherals. These dividers are part of the 16 PMU, and thus this node should be a child of the PMU node. 17 18 The following clocks are provided: 19 20 ID Clock 21 ------------- 22 0 AXI bus clock 23 1 GPU clock 24 2 VMeta clock 25 3 LCD clock 26 27properties: 28 compatible: 29 const: marvell,dove-divider-clock 30 31 reg: 32 maxItems: 1 33 34 '#clock-cells': 35 const: 1 36 37required: 38 - compatible 39 - reg 40 - '#clock-cells' 41 42additionalProperties: false 43 44examples: 45 - | 46 clock-controller@64 { 47 compatible = "marvell,dove-divider-clock"; 48 reg = <0x0064 0x8>; 49 #clock-cells = <1>; 50 }; 51