xref: /linux/Documentation/devicetree/bindings/clock/marvell,berlin2-clk.yaml (revision 8d2b0853add1d7534dc0794e3c8e0b9e8c4ec640) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/marvell,berlin2-clk.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Marvell Berlin Clock Controller
8
9maintainers:
10  - Jisheng Zhang <jszhang@kernel.org>
11
12description:
13  Clock related registers are spread among the chip control registers. Berlin
14  clock node should be a sub-node of the chip controller node. Marvell Berlin2
15  (BG2, BG2CD, BG2Q) SoCs share the same IP for PLLs and clocks, with some minor
16  differences in features and register layout.
17
18properties:
19  compatible:
20    enum:
21      - marvell,berlin2-clk
22      - marvell,berlin2q-clk
23
24  '#clock-cells':
25    const: 1
26
27  clocks:
28    maxItems: 1
29
30  clock-names:
31    items:
32      - enum:
33          - refclk
34          - video_ext0
35
36required:
37  - compatible
38  - '#clock-cells'
39  - clocks
40  - clock-names
41
42additionalProperties: false
43
44examples:
45  - |
46    clock-controller {
47        compatible = "marvell,berlin2q-clk";
48        #clock-cells = <1>;
49        clocks = <&refclk>;
50        clock-names = "refclk";
51    };
52