1*3b521bf8SLaurentiu Mihalcea# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*3b521bf8SLaurentiu Mihalcea%YAML 1.2 3*3b521bf8SLaurentiu Mihalcea--- 4*3b521bf8SLaurentiu Mihalcea$id: http://devicetree.org/schemas/clock/fsl,imx8ulp-sim-lpav.yaml# 5*3b521bf8SLaurentiu Mihalcea$schema: http://devicetree.org/meta-schemas/core.yaml# 6*3b521bf8SLaurentiu Mihalcea 7*3b521bf8SLaurentiu Mihalceatitle: NXP i.MX8ULP LPAV System Integration Module (SIM) 8*3b521bf8SLaurentiu Mihalcea 9*3b521bf8SLaurentiu Mihalceamaintainers: 10*3b521bf8SLaurentiu Mihalcea - Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com> 11*3b521bf8SLaurentiu Mihalcea 12*3b521bf8SLaurentiu Mihalceadescription: 13*3b521bf8SLaurentiu Mihalcea The i.MX8ULP LPAV subsystem contains a block control module known as 14*3b521bf8SLaurentiu Mihalcea SIM LPAV, which offers functionalities such as clock gating or reset 15*3b521bf8SLaurentiu Mihalcea line assertion/de-assertion. 16*3b521bf8SLaurentiu Mihalcea 17*3b521bf8SLaurentiu Mihalceaproperties: 18*3b521bf8SLaurentiu Mihalcea compatible: 19*3b521bf8SLaurentiu Mihalcea const: fsl,imx8ulp-sim-lpav 20*3b521bf8SLaurentiu Mihalcea 21*3b521bf8SLaurentiu Mihalcea reg: 22*3b521bf8SLaurentiu Mihalcea maxItems: 1 23*3b521bf8SLaurentiu Mihalcea 24*3b521bf8SLaurentiu Mihalcea clocks: 25*3b521bf8SLaurentiu Mihalcea maxItems: 3 26*3b521bf8SLaurentiu Mihalcea 27*3b521bf8SLaurentiu Mihalcea clock-names: 28*3b521bf8SLaurentiu Mihalcea items: 29*3b521bf8SLaurentiu Mihalcea - const: bus 30*3b521bf8SLaurentiu Mihalcea - const: core 31*3b521bf8SLaurentiu Mihalcea - const: plat 32*3b521bf8SLaurentiu Mihalcea 33*3b521bf8SLaurentiu Mihalcea '#clock-cells': 34*3b521bf8SLaurentiu Mihalcea const: 1 35*3b521bf8SLaurentiu Mihalcea 36*3b521bf8SLaurentiu Mihalcea '#reset-cells': 37*3b521bf8SLaurentiu Mihalcea const: 1 38*3b521bf8SLaurentiu Mihalcea 39*3b521bf8SLaurentiu Mihalcea mux-controller: 40*3b521bf8SLaurentiu Mihalcea $ref: /schemas/mux/reg-mux.yaml# 41*3b521bf8SLaurentiu Mihalcea 42*3b521bf8SLaurentiu Mihalcearequired: 43*3b521bf8SLaurentiu Mihalcea - compatible 44*3b521bf8SLaurentiu Mihalcea - reg 45*3b521bf8SLaurentiu Mihalcea - clocks 46*3b521bf8SLaurentiu Mihalcea - clock-names 47*3b521bf8SLaurentiu Mihalcea - '#clock-cells' 48*3b521bf8SLaurentiu Mihalcea - '#reset-cells' 49*3b521bf8SLaurentiu Mihalcea - mux-controller 50*3b521bf8SLaurentiu Mihalcea 51*3b521bf8SLaurentiu MihalceaadditionalProperties: false 52*3b521bf8SLaurentiu Mihalcea 53*3b521bf8SLaurentiu Mihalceaexamples: 54*3b521bf8SLaurentiu Mihalcea - | 55*3b521bf8SLaurentiu Mihalcea #include <dt-bindings/clock/imx8ulp-clock.h> 56*3b521bf8SLaurentiu Mihalcea 57*3b521bf8SLaurentiu Mihalcea clock-controller@2da50000 { 58*3b521bf8SLaurentiu Mihalcea compatible = "fsl,imx8ulp-sim-lpav"; 59*3b521bf8SLaurentiu Mihalcea reg = <0x2da50000 0x10000>; 60*3b521bf8SLaurentiu Mihalcea clocks = <&cgc2 IMX8ULP_CLK_LPAV_BUS_DIV>, 61*3b521bf8SLaurentiu Mihalcea <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>, 62*3b521bf8SLaurentiu Mihalcea <&cgc2 IMX8ULP_CLK_HIFI_DIVPLAT>; 63*3b521bf8SLaurentiu Mihalcea clock-names = "bus", "core", "plat"; 64*3b521bf8SLaurentiu Mihalcea #clock-cells = <1>; 65*3b521bf8SLaurentiu Mihalcea #reset-cells = <1>; 66*3b521bf8SLaurentiu Mihalcea 67*3b521bf8SLaurentiu Mihalcea mux-controller { 68*3b521bf8SLaurentiu Mihalcea compatible = "reg-mux"; 69*3b521bf8SLaurentiu Mihalcea #mux-control-cells = <1>; 70*3b521bf8SLaurentiu Mihalcea mux-reg-masks = <0x8 0x00000200>; 71*3b521bf8SLaurentiu Mihalcea }; 72*3b521bf8SLaurentiu Mihalcea }; 73