xref: /linux/Documentation/devicetree/bindings/clock/fsl,imx8ulp-sim-lpav.yaml (revision ba65a4e7120a616d9c592750d9147f6dcafedffa) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/fsl,imx8ulp-sim-lpav.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP i.MX8ULP LPAV System Integration Module (SIM)
8
9maintainers:
10  - Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
11
12description:
13  The i.MX8ULP LPAV subsystem contains a block control module known as
14  SIM LPAV, which offers functionalities such as clock gating or reset
15  line assertion/de-assertion.
16
17properties:
18  compatible:
19    const: fsl,imx8ulp-sim-lpav
20
21  reg:
22    maxItems: 1
23
24  clocks:
25    maxItems: 3
26
27  clock-names:
28    items:
29      - const: bus
30      - const: core
31      - const: plat
32
33  '#clock-cells':
34    const: 1
35
36  '#reset-cells':
37    const: 1
38
39  mux-controller:
40    $ref: /schemas/mux/reg-mux.yaml#
41
42required:
43  - compatible
44  - reg
45  - clocks
46  - clock-names
47  - '#clock-cells'
48  - '#reset-cells'
49  - mux-controller
50
51additionalProperties: false
52
53examples:
54  - |
55    #include <dt-bindings/clock/imx8ulp-clock.h>
56
57    clock-controller@2da50000 {
58        compatible = "fsl,imx8ulp-sim-lpav";
59        reg = <0x2da50000 0x10000>;
60        clocks = <&cgc2 IMX8ULP_CLK_LPAV_BUS_DIV>,
61                 <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>,
62                 <&cgc2 IMX8ULP_CLK_HIFI_DIVPLAT>;
63        clock-names = "bus", "core", "plat";
64        #clock-cells = <1>;
65        #reset-cells = <1>;
66
67        mux-controller {
68            compatible = "reg-mux";
69            #mux-control-cells = <1>;
70            mux-reg-masks = <0x8 0x00000200>;
71        };
72    };
73