1*fc8c21a2SXuyang Dong# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*fc8c21a2SXuyang Dong%YAML 1.2 3*fc8c21a2SXuyang Dong--- 4*fc8c21a2SXuyang Dong$id: http://devicetree.org/schemas/clock/eswin,eic7700-hspcrg.yaml# 5*fc8c21a2SXuyang Dong$schema: http://devicetree.org/meta-schemas/core.yaml# 6*fc8c21a2SXuyang Dong 7*fc8c21a2SXuyang Dongtitle: ESWIN EIC7700 HSP Clock and Reset Generator 8*fc8c21a2SXuyang Dong 9*fc8c21a2SXuyang Dongmaintainers: 10*fc8c21a2SXuyang Dong - Xuyang Dong <dongxuyang@eswincomputing.com> 11*fc8c21a2SXuyang Dong 12*fc8c21a2SXuyang Dongdescription: 13*fc8c21a2SXuyang Dong Clock and reset generator for the ESWIN EIC7700 HSP (high-speed peripherals). 14*fc8c21a2SXuyang Dong 15*fc8c21a2SXuyang Dongproperties: 16*fc8c21a2SXuyang Dong compatible: 17*fc8c21a2SXuyang Dong const: eswin,eic7700-hspcrg 18*fc8c21a2SXuyang Dong 19*fc8c21a2SXuyang Dong reg: 20*fc8c21a2SXuyang Dong maxItems: 1 21*fc8c21a2SXuyang Dong 22*fc8c21a2SXuyang Dong clocks: 23*fc8c21a2SXuyang Dong items: 24*fc8c21a2SXuyang Dong - description: HSP configuration top clock 25*fc8c21a2SXuyang Dong - description: MMC top clock 26*fc8c21a2SXuyang Dong - description: SATA top clock 27*fc8c21a2SXuyang Dong 28*fc8c21a2SXuyang Dong clock-names: 29*fc8c21a2SXuyang Dong items: 30*fc8c21a2SXuyang Dong - const: cfg 31*fc8c21a2SXuyang Dong - const: mmc 32*fc8c21a2SXuyang Dong - const: sata 33*fc8c21a2SXuyang Dong 34*fc8c21a2SXuyang Dong '#clock-cells': 35*fc8c21a2SXuyang Dong const: 1 36*fc8c21a2SXuyang Dong description: 37*fc8c21a2SXuyang Dong See <dt-bindings/clock/eswin,eic7700-hspcrg.h> for valid indices. 38*fc8c21a2SXuyang Dong 39*fc8c21a2SXuyang Dong '#reset-cells': 40*fc8c21a2SXuyang Dong const: 1 41*fc8c21a2SXuyang Dong description: 42*fc8c21a2SXuyang Dong See <dt-bindings/reset/eswin,eic7700-hspcrg.h> for valid indices. 43*fc8c21a2SXuyang Dong 44*fc8c21a2SXuyang Dongrequired: 45*fc8c21a2SXuyang Dong - compatible 46*fc8c21a2SXuyang Dong - reg 47*fc8c21a2SXuyang Dong - clocks 48*fc8c21a2SXuyang Dong - clock-names 49*fc8c21a2SXuyang Dong - '#clock-cells' 50*fc8c21a2SXuyang Dong - '#reset-cells' 51*fc8c21a2SXuyang Dong 52*fc8c21a2SXuyang DongadditionalProperties: false 53*fc8c21a2SXuyang Dong 54*fc8c21a2SXuyang Dongexamples: 55*fc8c21a2SXuyang Dong - | 56*fc8c21a2SXuyang Dong clock-controller@50440000 { 57*fc8c21a2SXuyang Dong compatible = "eswin,eic7700-hspcrg"; 58*fc8c21a2SXuyang Dong reg = <0x50440000 0x2000>; 59*fc8c21a2SXuyang Dong clocks = <&clock 171>, <&clock 254>, <&clock 187>; 60*fc8c21a2SXuyang Dong clock-names = "cfg", "mmc", "sata"; 61*fc8c21a2SXuyang Dong #clock-cells = <1>; 62*fc8c21a2SXuyang Dong #reset-cells = <1>; 63*fc8c21a2SXuyang Dong }; 64