xref: /linux/Documentation/devicetree/bindings/clock/axis,artpec9-clock.yaml (revision e65f4718a577fcc84d40431f022985898b6dbf2e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/axis,artpec9-clock.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Axis ARTPEC-9 SoC clock controller
8
9maintainers:
10  - Jesper Nilsson <jesper.nilsson@axis.com>
11
12description: |
13  ARTPEC-9 clock controller is comprised of several CMU (Clock Management Unit)
14  units, generating clocks for different domains. Those CMU units are modeled
15  as separate device tree nodes, and might depend on each other.
16  The root clock in that root tree is an external clock: OSCCLK (25 MHz).
17  This external clock must be defined as a fixed-rate clock in dts.
18
19  CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and
20  dividers, all other clocks of function blocks (other CMUs) are usually
21  derived from CMU_CMU.
22
23  Each clock is assigned an identifier and client nodes can use this identifier
24  to specify the clock which they consume. All clocks available for usage
25  in clock consumer nodes are defined as preprocessor macros in
26  'include/dt-bindings/clock/axis,artpec9-clk.h' header.
27
28properties:
29  compatible:
30    enum:
31      - axis,artpec9-cmu-cmu
32      - axis,artpec9-cmu-bus
33      - axis,artpec9-cmu-core
34      - axis,artpec9-cmu-cpucl
35      - axis,artpec9-cmu-fsys0
36      - axis,artpec9-cmu-fsys1
37      - axis,artpec9-cmu-imem
38      - axis,artpec9-cmu-peri
39
40  reg:
41    maxItems: 1
42
43  clocks:
44    minItems: 1
45    maxItems: 5
46
47  clock-names:
48    minItems: 1
49    maxItems: 5
50
51  "#clock-cells":
52    const: 1
53
54required:
55  - compatible
56  - reg
57  - clocks
58  - clock-names
59  - "#clock-cells"
60
61allOf:
62  - if:
63      properties:
64        compatible:
65          const: axis,artpec9-cmu-cmu
66
67    then:
68      properties:
69        clocks:
70          items:
71            - description: External reference clock (25 MHz)
72
73        clock-names:
74          items:
75            - const: fin_pll
76
77  - if:
78      properties:
79        compatible:
80          const: axis,artpec9-cmu-bus
81
82    then:
83      properties:
84        clocks:
85          items:
86            - description: External reference clock (25 MHz)
87            - description: CMU_BUS bus clock (from CMU_CMU)
88
89        clock-names:
90          items:
91            - const: fin_pll
92            - const: bus
93
94  - if:
95      properties:
96        compatible:
97          const: axis,artpec9-cmu-core
98
99    then:
100      properties:
101        clocks:
102          items:
103            - description: External reference clock (25 MHz)
104            - description: CMU_CORE main clock (from CMU_CMU)
105
106        clock-names:
107          items:
108            - const: fin_pll
109            - const: main
110
111  - if:
112      properties:
113        compatible:
114          const: axis,artpec9-cmu-cpucl
115
116    then:
117      properties:
118        clocks:
119          items:
120            - description: External reference clock (25 MHz)
121            - description: CMU_CPUCL switch clock (from CMU_CMU)
122
123        clock-names:
124          items:
125            - const: fin_pll
126            - const: switch
127
128  - if:
129      properties:
130        compatible:
131          const: axis,artpec9-cmu-fsys0
132
133    then:
134      properties:
135        clocks:
136          items:
137            - description: External reference clock (25 MHz)
138            - description: CMU_FSYS0 bus clock (from CMU_CMU)
139            - description: CMU_FSYS0 IP clock (from CMU_CMU)
140
141        clock-names:
142          items:
143            - const: fin_pll
144            - const: bus
145            - const: ip
146
147  - if:
148      properties:
149        compatible:
150          const: axis,artpec9-cmu-fsys1
151
152    then:
153      properties:
154        clocks:
155          items:
156            - description: External reference clock (25 MHz)
157            - description: CMU_FSYS1 scan0 clock (from CMU_CMU)
158            - description: CMU_FSYS1 scan1 clock (from CMU_CMU)
159            - description: CMU_FSYS1 bus clock (from CMU_CMU)
160
161        clock-names:
162          items:
163            - const: fin_pll
164            - const: scan0
165            - const: scan1
166            - const: bus
167
168  - if:
169      properties:
170        compatible:
171          const: axis,artpec9-cmu-imem
172
173    then:
174      properties:
175        clocks:
176          items:
177            - description: External reference clock (25 MHz)
178            - description: CMU_IMEM ACLK clock (from CMU_CMU)
179            - description: CMU_IMEM CA5 clock (from CMU_CMU)
180            - description: CMU_IMEM JPEG clock (from CMU_CMU)
181            - description: CMU_IMEM SSS clock (from CMU_CMU)
182
183        clock-names:
184          items:
185            - const: fin_pll
186            - const: aclk
187            - const: ca5
188            - const: jpeg
189            - const: sss
190
191  - if:
192      properties:
193        compatible:
194          const: axis,artpec9-cmu-peri
195
196    then:
197      properties:
198        clocks:
199          items:
200            - description: External reference clock (25 MHz)
201            - description: CMU_PERI IP clock (from CMU_CMU)
202            - description: CMU_PERI DISP clock (from CMU_CMU)
203
204        clock-names:
205          items:
206            - const: fin_pll
207            - const: ip
208            - const: disp
209
210additionalProperties: false
211
212examples:
213  # Clock controller node for CMU_FSYS1
214  - |
215    #include <dt-bindings/clock/axis,artpec9-clk.h>
216
217    soc {
218        #address-cells = <2>;
219        #size-cells = <2>;
220
221        cmu_fsys1: clock-controller@14c10000 {
222            compatible = "axis,artpec9-cmu-fsys1";
223            reg = <0x0 0x14c10000 0x0 0x4000>;
224            #clock-cells = <1>;
225            clocks = <&fin_pll>,
226                     <&cmu_cmu CLK_DOUT_CMU_FSYS1_SCAN0>,
227                     <&cmu_cmu CLK_DOUT_CMU_FSYS1_SCAN1>,
228                     <&cmu_cmu CLK_DOUT_CMU_FSYS1_BUS>;
229            clock-names = "fin_pll", "scan0", "scan1", "bus";
230        };
231    };
232...
233