1*094e1118SRob Herring (Arm)# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*094e1118SRob Herring (Arm)%YAML 1.2 3*094e1118SRob Herring (Arm)--- 4*094e1118SRob Herring (Arm)$id: http://devicetree.org/schemas/clock/apm,xgene-device-clock.yaml# 5*094e1118SRob Herring (Arm)$schema: http://devicetree.org/meta-schemas/core.yaml# 6*094e1118SRob Herring (Arm) 7*094e1118SRob Herring (Arm)title: APM X-Gene SoC device clocks 8*094e1118SRob Herring (Arm) 9*094e1118SRob Herring (Arm)maintainers: 10*094e1118SRob Herring (Arm) - Khuong Dinh <khuong@os.amperecomputing.com> 11*094e1118SRob Herring (Arm) 12*094e1118SRob Herring (Arm)properties: 13*094e1118SRob Herring (Arm) compatible: 14*094e1118SRob Herring (Arm) const: apm,xgene-device-clock 15*094e1118SRob Herring (Arm) 16*094e1118SRob Herring (Arm) reg: 17*094e1118SRob Herring (Arm) minItems: 1 18*094e1118SRob Herring (Arm) maxItems: 2 19*094e1118SRob Herring (Arm) 20*094e1118SRob Herring (Arm) reg-names: 21*094e1118SRob Herring (Arm) items: 22*094e1118SRob Herring (Arm) - enum: [ csr-reg, div-reg ] 23*094e1118SRob Herring (Arm) - const: div-reg 24*094e1118SRob Herring (Arm) minItems: 1 25*094e1118SRob Herring (Arm) 26*094e1118SRob Herring (Arm) clocks: 27*094e1118SRob Herring (Arm) maxItems: 1 28*094e1118SRob Herring (Arm) 29*094e1118SRob Herring (Arm) "#clock-cells": 30*094e1118SRob Herring (Arm) const: 1 31*094e1118SRob Herring (Arm) 32*094e1118SRob Herring (Arm) clock-output-names: 33*094e1118SRob Herring (Arm) maxItems: 1 34*094e1118SRob Herring (Arm) 35*094e1118SRob Herring (Arm) clock-names: 36*094e1118SRob Herring (Arm) maxItems: 1 37*094e1118SRob Herring (Arm) 38*094e1118SRob Herring (Arm) csr-offset: 39*094e1118SRob Herring (Arm) description: Offset to the CSR reset register 40*094e1118SRob Herring (Arm) $ref: /schemas/types.yaml#/definitions/uint32 41*094e1118SRob Herring (Arm) default: 0 42*094e1118SRob Herring (Arm) 43*094e1118SRob Herring (Arm) csr-mask: 44*094e1118SRob Herring (Arm) description: CSR reset mask bit 45*094e1118SRob Herring (Arm) $ref: /schemas/types.yaml#/definitions/uint32 46*094e1118SRob Herring (Arm) default: 0xf 47*094e1118SRob Herring (Arm) 48*094e1118SRob Herring (Arm) enable-offset: 49*094e1118SRob Herring (Arm) description: Offset to the enable register 50*094e1118SRob Herring (Arm) $ref: /schemas/types.yaml#/definitions/uint32 51*094e1118SRob Herring (Arm) default: 8 52*094e1118SRob Herring (Arm) 53*094e1118SRob Herring (Arm) enable-mask: 54*094e1118SRob Herring (Arm) description: CSR enable mask bit 55*094e1118SRob Herring (Arm) $ref: /schemas/types.yaml#/definitions/uint32 56*094e1118SRob Herring (Arm) default: 0xf 57*094e1118SRob Herring (Arm) 58*094e1118SRob Herring (Arm) divider-offset: 59*094e1118SRob Herring (Arm) description: Offset to the divider register 60*094e1118SRob Herring (Arm) $ref: /schemas/types.yaml#/definitions/uint32 61*094e1118SRob Herring (Arm) default: 0 62*094e1118SRob Herring (Arm) 63*094e1118SRob Herring (Arm) divider-width: 64*094e1118SRob Herring (Arm) description: Width of the divider register 65*094e1118SRob Herring (Arm) $ref: /schemas/types.yaml#/definitions/uint32 66*094e1118SRob Herring (Arm) default: 0 67*094e1118SRob Herring (Arm) 68*094e1118SRob Herring (Arm) divider-shift: 69*094e1118SRob Herring (Arm) description: Bit shift of the divider register 70*094e1118SRob Herring (Arm) $ref: /schemas/types.yaml#/definitions/uint32 71*094e1118SRob Herring (Arm) default: 0 72*094e1118SRob Herring (Arm) 73*094e1118SRob Herring (Arm)required: 74*094e1118SRob Herring (Arm) - compatible 75*094e1118SRob Herring (Arm) - reg 76*094e1118SRob Herring (Arm) - clocks 77*094e1118SRob Herring (Arm) - '#clock-cells' 78*094e1118SRob Herring (Arm) - clock-output-names 79*094e1118SRob Herring (Arm) 80*094e1118SRob Herring (Arm)additionalProperties: false 81