1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/apm,xgene-device-clock.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: APM X-Gene SoC device clocks 8 9maintainers: 10 - Khuong Dinh <khuong@os.amperecomputing.com> 11 12properties: 13 compatible: 14 const: apm,xgene-device-clock 15 16 reg: 17 minItems: 1 18 maxItems: 2 19 20 reg-names: 21 items: 22 - enum: [ csr-reg, div-reg ] 23 - const: div-reg 24 minItems: 1 25 26 clocks: 27 maxItems: 1 28 29 "#clock-cells": 30 const: 1 31 32 clock-output-names: 33 maxItems: 1 34 35 clock-names: 36 maxItems: 1 37 38 csr-offset: 39 description: Offset to the CSR reset register 40 $ref: /schemas/types.yaml#/definitions/uint32 41 default: 0 42 43 csr-mask: 44 description: CSR reset mask bit 45 $ref: /schemas/types.yaml#/definitions/uint32 46 default: 0xf 47 48 enable-offset: 49 description: Offset to the enable register 50 $ref: /schemas/types.yaml#/definitions/uint32 51 default: 8 52 53 enable-mask: 54 description: CSR enable mask bit 55 $ref: /schemas/types.yaml#/definitions/uint32 56 default: 0xf 57 58 divider-offset: 59 description: Offset to the divider register 60 $ref: /schemas/types.yaml#/definitions/uint32 61 default: 0 62 63 divider-width: 64 description: Width of the divider register 65 $ref: /schemas/types.yaml#/definitions/uint32 66 default: 0 67 68 divider-shift: 69 description: Bit shift of the divider register 70 $ref: /schemas/types.yaml#/definitions/uint32 71 default: 0 72 73required: 74 - compatible 75 - reg 76 - clocks 77 - '#clock-cells' 78 - clock-output-names 79 80additionalProperties: false 81