xref: /linux/Documentation/devicetree/bindings/clock/amlogic,a9-peripherals-clkc.yaml (revision 502d45774af09f1c681c754c4b7cdfb5d7f72fd9) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2026 Amlogic, Inc. All rights reserved
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/clock/amlogic,a9-peripherals-clkc.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Amlogic A9 Series Peripherals Clock Controller
9
10maintainers:
11  - Neil Armstrong <neil.armstrong@linaro.org>
12  - Jerome Brunet <jbrunet@baylibre.com>
13  - Jian Hu <jian.hu@amlogic.com>
14  - Xianwei Zhao <xianwei.zhao@amlogic.com>
15
16properties:
17  compatible:
18    const: amlogic,a9-peripherals-clkc
19
20  reg:
21    maxItems: 1
22
23  '#clock-cells':
24    const: 1
25
26  clocks:
27    minItems: 27
28    items:
29      - description: input oscillator
30      - description: input fclk div 2
31      - description: input fclk div 3
32      - description: input fclk div 4
33      - description: input fclk div 5
34      - description: input fclk div 7
35      - description: input fclk div 2p5
36      - description: input sys clk
37      - description: input gp1 pll
38      - description: input gp2 pll
39      - description: input sys pll div 16
40      - description: input cpu clk div 16
41      - description: input a78 clk div 16
42      - description: input dsu clk div 16
43      - description: input rtc clk
44      - description: input gp0 pll
45      - description: input hifi0 pll
46      - description: input hifi1 pll
47      - description: input mclk0 pll
48      - description: input mclk1 pll
49      - description: input video1 pll
50      - description: input video2 pll
51      - description: input hdmi out2 clk
52      - description: input hdmi pixel clk
53      - description: input pixel0 pll
54      - description: input pixel1 pll
55      - description: input ddr pll test clk
56      - description: external input rmii oscillator (optional)
57
58  clock-names:
59    minItems: 27
60    items:
61      - const: xtal
62      - const: fdiv2
63      - const: fdiv3
64      - const: fdiv4
65      - const: fdiv5
66      - const: fdiv7
67      - const: fdiv2p5
68      - const: sys
69      - const: gp1
70      - const: gp2
71      - const: sysplldiv16
72      - const: cpudiv16
73      - const: a78div16
74      - const: dsudiv16
75      - const: rtc
76      - const: gp0
77      - const: hifi0
78      - const: hifi1
79      - const: mclk0
80      - const: mclk1
81      - const: vid1
82      - const: vid2
83      - const: hdmiout2
84      - const: hdmipix
85      - const: pix0
86      - const: pix1
87      - const: ddr_test
88      - const: ext_rmii
89
90required:
91  - compatible
92  - reg
93  - '#clock-cells'
94  - clocks
95  - clock-names
96
97additionalProperties: false
98
99examples:
100  - |
101    soc {
102        #address-cells = <2>;
103        #size-cells = <2>;
104
105        clock-controller@200 {
106            compatible = "amlogic,a9-peripherals-clkc";
107            reg = <0x0 0x200 0x0 0x2f8>;
108            #clock-cells = <1>;
109            clocks = <&xtal>,
110                     <&scmi_clk 10>,
111                     <&scmi_clk 12>,
112                     <&scmi_clk 14>,
113                     <&scmi_clk 16>,
114                     <&scmi_clk 18>,
115                     <&scmi_clk 20>,
116                     <&scmi_clk 21>,
117                     <&scmi_clk 33>,
118                     <&scmi_clk 34>,
119                     <&scmi_clk 35>,
120                     <&scmi_clk 36>,
121                     <&scmi_clk 37>,
122                     <&scmi_clk 38>,
123                     <&scmi_clk 40>,
124                     <&gp0 3>,
125                     <&hifi0 3>,
126                     <&hifi1 3>,
127                     <&mclk0 3>,
128                     <&mclk1 3>,
129                     <&vid1>,
130                     <&vid2>,
131                     <&hdmitx 10>,
132                     <&hdmitx 11>,
133                     <&pix0>,
134                     <&pix1>,
135                     <&ddr 3>;
136            clock-names = "xtal",
137                          "fdiv2",
138                          "fdiv3",
139                          "fdiv4",
140                          "fdiv5",
141                          "fdiv7",
142                          "fdiv2p5",
143                          "sys",
144                          "gp1",
145                          "gp2",
146                          "sysplldiv16",
147                          "cpudiv16",
148                          "a78div16",
149                          "dsudiv16",
150                          "rtc",
151                          "gp0",
152                          "hifi0",
153                          "hifi1",
154                          "mclk0",
155                          "mclk1",
156                          "vid1",
157                          "vid2",
158                          "hdmiout2",
159                          "hdmipix",
160                          "pix0",
161                          "pix1",
162                          "ddr_test";
163        };
164    };
165