1What: /sys/bus/cxl/flush 2Date: Januarry, 2022 3KernelVersion: v5.18 4Contact: linux-cxl@vger.kernel.org 5Description: 6 (WO) If userspace manually unbinds a port the kernel schedules 7 all descendant memdevs for unbind. Writing '1' to this attribute 8 flushes that work. 9 10What: /sys/bus/cxl/devices/memX/firmware_version 11Date: December, 2020 12KernelVersion: v5.12 13Contact: linux-cxl@vger.kernel.org 14Description: 15 (RO) "FW Revision" string as reported by the Identify 16 Memory Device Output Payload in the CXL-2.0 17 specification. 18 19What: /sys/bus/cxl/devices/memX/ram/size 20Date: December, 2020 21KernelVersion: v5.12 22Contact: linux-cxl@vger.kernel.org 23Description: 24 (RO) "Volatile Only Capacity" as bytes. Represents the 25 identically named field in the Identify Memory Device Output 26 Payload in the CXL-2.0 specification. 27 28What: /sys/bus/cxl/devices/memX/pmem/size 29Date: December, 2020 30KernelVersion: v5.12 31Contact: linux-cxl@vger.kernel.org 32Description: 33 (RO) "Persistent Only Capacity" as bytes. Represents the 34 identically named field in the Identify Memory Device Output 35 Payload in the CXL-2.0 specification. 36 37What: /sys/bus/cxl/devices/memX/serial 38Date: January, 2022 39KernelVersion: v5.18 40Contact: linux-cxl@vger.kernel.org 41Description: 42 (RO) 64-bit serial number per the PCIe Device Serial Number 43 capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2 44 Memory Device PCIe Capabilities and Extended Capabilities. 45 46What: /sys/bus/cxl/devices/memX/numa_node 47Date: January, 2022 48KernelVersion: v5.18 49Contact: linux-cxl@vger.kernel.org 50Description: 51 (RO) If NUMA is enabled and the platform has affinitized the 52 host PCI device for this memory device, emit the CPU node 53 affinity for this device. 54 55What: /sys/bus/cxl/devices/*/devtype 56Date: June, 2021 57KernelVersion: v5.14 58Contact: linux-cxl@vger.kernel.org 59Description: 60 CXL device objects export the devtype attribute which mirrors 61 the same value communicated in the DEVTYPE environment variable 62 for uevents for devices on the "cxl" bus. 63 64What: /sys/bus/cxl/devices/*/modalias 65Date: December, 2021 66KernelVersion: v5.18 67Contact: linux-cxl@vger.kernel.org 68Description: 69 CXL device objects export the modalias attribute which mirrors 70 the same value communicated in the MODALIAS environment variable 71 for uevents for devices on the "cxl" bus. 72 73What: /sys/bus/cxl/devices/portX/uport 74Date: June, 2021 75KernelVersion: v5.14 76Contact: linux-cxl@vger.kernel.org 77Description: 78 CXL port objects are enumerated from either a platform firmware 79 device (ACPI0017 and ACPI0016) or PCIe switch upstream port with 80 CXL component registers. The 'uport' symlink connects the CXL 81 portX object to the device that published the CXL port 82 capability. 83 84What: /sys/bus/cxl/devices/portX/dportY 85Date: June, 2021 86KernelVersion: v5.14 87Contact: linux-cxl@vger.kernel.org 88Description: 89 CXL port objects are enumerated from either a platform firmware 90 device (ACPI0017 and ACPI0016) or PCIe switch upstream port with 91 CXL component registers. The 'dportY' symlink identifies one or 92 more downstream ports that the upstream port may target in its 93 decode of CXL memory resources. The 'Y' integer reflects the 94 hardware port unique-id used in the hardware decoder target 95 list. 96 97What: /sys/bus/cxl/devices/decoderX.Y 98Date: June, 2021 99KernelVersion: v5.14 100Contact: linux-cxl@vger.kernel.org 101Description: 102 CXL decoder objects are enumerated from either a platform 103 firmware description, or a CXL HDM decoder register set in a 104 PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder 105 Capability Structure). The 'X' in decoderX.Y represents the 106 cxl_port container of this decoder, and 'Y' represents the 107 instance id of a given decoder resource. 108 109What: /sys/bus/cxl/devices/decoderX.Y/{start,size} 110Date: June, 2021 111KernelVersion: v5.14 112Contact: linux-cxl@vger.kernel.org 113Description: 114 The 'start' and 'size' attributes together convey the physical 115 address base and number of bytes mapped in the decoder's decode 116 window. For decoders of devtype "cxl_decoder_root" the address 117 range is fixed. For decoders of devtype "cxl_decoder_switch" the 118 address is bounded by the decode range of the cxl_port ancestor 119 of the decoder's cxl_port, and dynamically updates based on the 120 active memory regions in that address space. 121 122What: /sys/bus/cxl/devices/decoderX.Y/locked 123Date: June, 2021 124KernelVersion: v5.14 125Contact: linux-cxl@vger.kernel.org 126Description: 127 CXL HDM decoders have the capability to lock the configuration 128 until the next device reset. For decoders of devtype 129 "cxl_decoder_root" there is no standard facility to unlock them. 130 For decoders of devtype "cxl_decoder_switch" a secondary bus 131 reset, of the PCIe bridge that provides the bus for this 132 decoders uport, unlocks / resets the decoder. 133 134What: /sys/bus/cxl/devices/decoderX.Y/target_list 135Date: June, 2021 136KernelVersion: v5.14 137Contact: linux-cxl@vger.kernel.org 138Description: 139 Display a comma separated list of the current decoder target 140 configuration. The list is ordered by the current configured 141 interleave order of the decoder's dport instances. Each entry in 142 the list is a dport id. 143 144What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3} 145Date: June, 2021 146KernelVersion: v5.14 147Contact: linux-cxl@vger.kernel.org 148Description: 149 When a CXL decoder is of devtype "cxl_decoder_root", it 150 represents a fixed memory window identified by platform 151 firmware. A fixed window may only support a subset of memory 152 types. The 'cap_*' attributes indicate whether persistent 153 memory, volatile memory, accelerator memory, and / or expander 154 memory may be mapped behind this decoder's memory window. 155 156What: /sys/bus/cxl/devices/decoderX.Y/target_type 157Date: June, 2021 158KernelVersion: v5.14 159Contact: linux-cxl@vger.kernel.org 160Description: 161 When a CXL decoder is of devtype "cxl_decoder_switch", it can 162 optionally decode either accelerator memory (type-2) or expander 163 memory (type-3). The 'target_type' attribute indicates the 164 current setting which may dynamically change based on what 165 memory regions are activated in this decode hierarchy. 166