1What: /sys/bus/cxl/flush 2Date: January, 2022 3KernelVersion: v5.18 4Contact: linux-cxl@vger.kernel.org 5Description: 6 (WO) If userspace manually unbinds a port the kernel schedules 7 all descendant memdevs for unbind. Writing '1' to this attribute 8 flushes that work. 9 10 11What: /sys/bus/cxl/devices/memX/firmware_version 12Date: December, 2020 13KernelVersion: v5.12 14Contact: linux-cxl@vger.kernel.org 15Description: 16 (RO) "FW Revision" string as reported by the Identify 17 Memory Device Output Payload in the CXL-2.0 18 specification. 19 20 21What: /sys/bus/cxl/devices/memX/payload_max 22Date: December, 2020 23KernelVersion: v5.12 24Contact: linux-cxl@vger.kernel.org 25Description: 26 (RO) Maximum size (in bytes) of the mailbox command payload 27 registers. Linux caps this at 1MB if the device reports a 28 larger size. 29 30 31What: /sys/bus/cxl/devices/memX/label_storage_size 32Date: May, 2021 33KernelVersion: v5.13 34Contact: linux-cxl@vger.kernel.org 35Description: 36 (RO) Size (in bytes) of the Label Storage Area (LSA). 37 38 39What: /sys/bus/cxl/devices/memX/ram/size 40Date: December, 2020 41KernelVersion: v5.12 42Contact: linux-cxl@vger.kernel.org 43Description: 44 (RO) "Volatile Only Capacity" as bytes. Represents the 45 identically named field in the Identify Memory Device Output 46 Payload in the CXL-2.0 specification. 47 48 49What: /sys/bus/cxl/devices/memX/ram/qos_class 50Date: May, 2023 51KernelVersion: v6.8 52Contact: linux-cxl@vger.kernel.org 53Description: 54 (RO) For CXL host platforms that support "QoS Telemetry" 55 this attribute conveys a comma delimited list of platform 56 specific cookies that identifies a QoS performance class 57 for the volatile partition of the CXL mem device. These 58 class-ids can be compared against a similar "qos_class" 59 published for a root decoder. While it is not required 60 that the endpoints map their local memory-class to a 61 matching platform class, mismatches are not recommended 62 and there are platform specific performance related 63 side-effects that may result. First class-id is displayed. 64 65 66What: /sys/bus/cxl/devices/memX/pmem/size 67Date: December, 2020 68KernelVersion: v5.12 69Contact: linux-cxl@vger.kernel.org 70Description: 71 (RO) "Persistent Only Capacity" as bytes. Represents the 72 identically named field in the Identify Memory Device Output 73 Payload in the CXL-2.0 specification. 74 75 76What: /sys/bus/cxl/devices/memX/pmem/qos_class 77Date: May, 2023 78KernelVersion: v6.8 79Contact: linux-cxl@vger.kernel.org 80Description: 81 (RO) For CXL host platforms that support "QoS Telemetry" 82 this attribute conveys a comma delimited list of platform 83 specific cookies that identifies a QoS performance class 84 for the persistent partition of the CXL mem device. These 85 class-ids can be compared against a similar "qos_class" 86 published for a root decoder. While it is not required 87 that the endpoints map their local memory-class to a 88 matching platform class, mismatches are not recommended 89 and there are platform specific performance related 90 side-effects that may result. First class-id is displayed. 91 92 93What: /sys/bus/cxl/devices/memX/serial 94Date: January, 2022 95KernelVersion: v5.18 96Contact: linux-cxl@vger.kernel.org 97Description: 98 (RO) 64-bit serial number per the PCIe Device Serial Number 99 capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2 100 Memory Device PCIe Capabilities and Extended Capabilities. 101 102 103What: /sys/bus/cxl/devices/memX/numa_node 104Date: January, 2022 105KernelVersion: v5.18 106Contact: linux-cxl@vger.kernel.org 107Description: 108 (RO) If NUMA is enabled and the platform has affinitized the 109 host PCI device for this memory device, emit the CPU node 110 affinity for this device. 111 112 113What: /sys/bus/cxl/devices/memX/security/state 114Date: June, 2023 115KernelVersion: v6.5 116Contact: linux-cxl@vger.kernel.org 117Description: 118 (RO) Reading this file will display the CXL security state for 119 that device. Such states can be: 'disabled', 'sanitize', when 120 a sanitization is currently underway; or those available only 121 for persistent memory: 'locked', 'unlocked' or 'frozen'. This 122 sysfs entry is select/poll capable from userspace to notify 123 upon completion of a sanitize operation. 124 125 126What: /sys/bus/cxl/devices/memX/security/sanitize 127Date: June, 2023 128KernelVersion: v6.5 129Contact: linux-cxl@vger.kernel.org 130Description: 131 (WO) Write a boolean 'true' string value to this attribute to 132 sanitize the device to securely re-purpose or decommission it. 133 This is done by ensuring that all user data and meta-data, 134 whether it resides in persistent capacity, volatile capacity, 135 or the LSA, is made permanently unavailable by whatever means 136 is appropriate for the media type. This functionality requires 137 the device to be disabled, that is, not actively decoding any 138 HPA ranges. This permits avoiding explicit global CPU cache 139 management, relying instead for it to be done when a region 140 transitions between software programmed and hardware committed 141 states. If this file is not present, then there is no hardware 142 support for the operation. 143 144 145What /sys/bus/cxl/devices/memX/security/erase 146Date: June, 2023 147KernelVersion: v6.5 148Contact: linux-cxl@vger.kernel.org 149Description: 150 (WO) Write a boolean 'true' string value to this attribute to 151 secure erase user data by changing the media encryption keys for 152 all user data areas of the device. This functionality requires 153 the device to be disabled, that is, not actively decoding any 154 HPA ranges. This permits avoiding explicit global CPU cache 155 management, relying instead for it to be done when a region 156 transitions between software programmed and hardware committed 157 states. If this file is not present, then there is no hardware 158 support for the operation. 159 160 161What: /sys/bus/cxl/devices/memX/firmware/ 162Date: April, 2023 163KernelVersion: v6.5 164Contact: linux-cxl@vger.kernel.org 165Description: 166 (RW) Firmware uploader mechanism. The different files under 167 this directory can be used to upload and activate new 168 firmware for CXL devices. The interfaces under this are 169 documented in sysfs-class-firmware. 170 171 172What: /sys/bus/cxl/devices/*/devtype 173Date: June, 2021 174KernelVersion: v5.14 175Contact: linux-cxl@vger.kernel.org 176Description: 177 (RO) CXL device objects export the devtype attribute which 178 mirrors the same value communicated in the DEVTYPE environment 179 variable for uevents for devices on the "cxl" bus. 180 181 182What: /sys/bus/cxl/devices/*/modalias 183Date: December, 2021 184KernelVersion: v5.18 185Contact: linux-cxl@vger.kernel.org 186Description: 187 (RO) CXL device objects export the modalias attribute which 188 mirrors the same value communicated in the MODALIAS environment 189 variable for uevents for devices on the "cxl" bus. 190 191 192What: /sys/bus/cxl/devices/portX/uport 193Date: June, 2021 194KernelVersion: v5.14 195Contact: linux-cxl@vger.kernel.org 196Description: 197 (RO) CXL port objects are enumerated from either a platform 198 firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream 199 port with CXL component registers. The 'uport' symlink connects 200 the CXL portX object to the device that published the CXL port 201 capability. 202 203 204What: /sys/bus/cxl/devices/portX/parent_dport 205What: /sys/bus/cxl/devices/endpointX/parent_dport 206Date: January, 2023 207KernelVersion: v6.3 208Contact: linux-cxl@vger.kernel.org 209Description: 210 (RO) CXL port objects are instantiated for each upstream port in 211 a CXL/PCIe switch, and for each endpoint to map the 212 corresponding memory device into the CXL port hierarchy. When a 213 descendant CXL port (switch or endpoint) is enumerated it is 214 useful to know which 'dport' object in the parent CXL port 215 routes to this descendant. The 'parent_dport' symlink points to 216 the device representing the downstream port of a CXL switch that 217 routes to {port,endpoint}X. 218 219 220What: /sys/bus/cxl/devices/portX/dportY 221Date: June, 2021 222KernelVersion: v5.14 223Contact: linux-cxl@vger.kernel.org 224Description: 225 (RO) CXL port objects are enumerated from either a platform 226 firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream 227 port with CXL component registers. The 'dportY' symlink 228 identifies one or more downstream ports that the upstream port 229 may target in its decode of CXL memory resources. The 'Y' 230 integer reflects the hardware port unique-id used in the 231 hardware decoder target list. 232 233 234What: /sys/bus/cxl/devices/portX/decoders_committed 235Date: October, 2023 236KernelVersion: v6.7 237Contact: linux-cxl@vger.kernel.org 238Description: 239 (RO) A memory device is considered active when any of its 240 decoders are in the "committed" state (See CXL 3.0 8.2.4.19.7 241 CXL HDM Decoder n Control Register). Hotplug and destructive 242 operations like "sanitize" are blocked while device is actively 243 decoding a Host Physical Address range. Note that this number 244 may be elevated without any regionX objects active or even 245 enumerated, as this may be due to decoders established by 246 platform firmware or a previous kernel (kexec). 247 248 249What: /sys/bus/cxl/devices/decoderX.Y 250Date: June, 2021 251KernelVersion: v5.14 252Contact: linux-cxl@vger.kernel.org 253Description: 254 (RO) CXL decoder objects are enumerated from either a platform 255 firmware description, or a CXL HDM decoder register set in a 256 PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder 257 Capability Structure). The 'X' in decoderX.Y represents the 258 cxl_port container of this decoder, and 'Y' represents the 259 instance id of a given decoder resource. 260 261 262What: /sys/bus/cxl/devices/decoderX.Y/start 263What: /sys/bus/cxl/devices/decoderX.Y/size 264Date: June, 2021 265KernelVersion: v5.14 266Contact: linux-cxl@vger.kernel.org 267Description: 268 (RO) The 'start' and 'size' attributes together convey the 269 physical address base and number of bytes mapped in the 270 decoder's decode window. For decoders of devtype 271 "cxl_decoder_root" the address range is fixed. For decoders of 272 devtype "cxl_decoder_switch" the address is bounded by the 273 decode range of the cxl_port ancestor of the decoder's cxl_port, 274 and dynamically updates based on the active memory regions in 275 that address space. 276 277 278What: /sys/bus/cxl/devices/decoderX.Y/locked 279Date: June, 2021 280KernelVersion: v5.14 281Contact: linux-cxl@vger.kernel.org 282Description: 283 (RO) CXL HDM decoders have the capability to lock the 284 configuration until the next device reset. For decoders of 285 devtype "cxl_decoder_root" there is no standard facility to 286 unlock them. For decoders of devtype "cxl_decoder_switch" a 287 secondary bus reset, of the PCIe bridge that provides the bus 288 for this decoders uport, unlocks / resets the decoder. 289 290 291What: /sys/bus/cxl/devices/decoderX.Y/target_list 292Date: June, 2021 293KernelVersion: v5.14 294Contact: linux-cxl@vger.kernel.org 295Description: 296 (RO) Display a comma separated list of the current decoder 297 target configuration. The list is ordered by the current 298 configured interleave order of the decoder's dport instances. 299 Each entry in the list is a dport id. 300 301 302What: /sys/bus/cxl/devices/decoderX.Y/cap_pmem 303What: /sys/bus/cxl/devices/decoderX.Y/cap_ram 304What: /sys/bus/cxl/devices/decoderX.Y/cap_type2 305What: /sys/bus/cxl/devices/decoderX.Y/cap_type3 306Date: June, 2021 307KernelVersion: v5.14 308Contact: linux-cxl@vger.kernel.org 309Description: 310 (RO) When a CXL decoder is of devtype "cxl_decoder_root", it 311 represents a fixed memory window identified by platform 312 firmware. A fixed window may only support a subset of memory 313 types. The 'cap_*' attributes indicate whether persistent 314 memory, volatile memory, accelerator memory, and / or expander 315 memory may be mapped behind this decoder's memory window. 316 317 318What: /sys/bus/cxl/devices/decoderX.Y/target_type 319Date: June, 2021 320KernelVersion: v5.14 321Contact: linux-cxl@vger.kernel.org 322Description: 323 (RO) When a CXL decoder is of devtype "cxl_decoder_switch", it 324 can optionally decode either accelerator memory (type-2) or 325 expander memory (type-3). The 'target_type' attribute indicates 326 the current setting which may dynamically change based on what 327 memory regions are activated in this decode hierarchy. 328 329 330What: /sys/bus/cxl/devices/endpointX/CDAT 331Date: July, 2022 332KernelVersion: v6.0 333Contact: linux-cxl@vger.kernel.org 334Description: 335 (RO) If this sysfs entry is not present no DOE mailbox was 336 found to support CDAT data. If it is present and the length of 337 the data is 0 reading the CDAT data failed. Otherwise the CDAT 338 data is reported. 339 340 341What: /sys/bus/cxl/devices/decoderX.Y/mode 342Date: May, 2022 343KernelVersion: v6.0 344Contact: linux-cxl@vger.kernel.org 345Description: 346 (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it 347 translates from a host physical address range, to a device 348 local address range. Device-local address ranges are further 349 split into a 'ram' (volatile memory) range and 'pmem' 350 (persistent memory) range. The 'mode' attribute emits one of 351 'ram', 'pmem', or 'none'. The 'none' indicates the decoder is 352 not actively decoding, or no DPA allocation policy has been 353 set. 354 355 'mode' can be written, when the decoder is in the 'disabled' 356 state, with either 'ram' or 'pmem' to set the boundaries for the 357 next allocation. 358 359 360What: /sys/bus/cxl/devices/decoderX.Y/dpa_resource 361Date: May, 2022 362KernelVersion: v6.0 363Contact: linux-cxl@vger.kernel.org 364Description: 365 (RO) When a CXL decoder is of devtype "cxl_decoder_endpoint", 366 and its 'dpa_size' attribute is non-zero, this attribute 367 indicates the device physical address (DPA) base address of the 368 allocation. 369 370 371What: /sys/bus/cxl/devices/decoderX.Y/dpa_size 372Date: May, 2022 373KernelVersion: v6.0 374Contact: linux-cxl@vger.kernel.org 375Description: 376 (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it 377 translates from a host physical address range, to a device local 378 address range. The range, base address plus length in bytes, of 379 DPA allocated to this decoder is conveyed in these 2 attributes. 380 Allocations can be mutated as long as the decoder is in the 381 disabled state. A write to 'dpa_size' releases the previous DPA 382 allocation and then attempts to allocate from the free capacity 383 in the device partition referred to by 'decoderX.Y/mode'. 384 Allocate and free requests can only be performed on the highest 385 instance number disabled decoder with non-zero size. I.e. 386 allocations are enforced to occur in increasing 'decoderX.Y/id' 387 order and frees are enforced to occur in decreasing 388 'decoderX.Y/id' order. 389 390 391What: /sys/bus/cxl/devices/decoderX.Y/interleave_ways 392Date: May, 2022 393KernelVersion: v6.0 394Contact: linux-cxl@vger.kernel.org 395Description: 396 (RO) The number of targets across which this decoder's host 397 physical address (HPA) memory range is interleaved. The device 398 maps every Nth block of HPA (of size == 399 'interleave_granularity') to consecutive DPA addresses. The 400 decoder's position in the interleave is determined by the 401 device's (endpoint or switch) switch ancestry. For root 402 decoders their interleave is specified by platform firmware and 403 they only specify a downstream target order for host bridges. 404 405 406What: /sys/bus/cxl/devices/decoderX.Y/interleave_granularity 407Date: May, 2022 408KernelVersion: v6.0 409Contact: linux-cxl@vger.kernel.org 410Description: 411 (RO) The number of consecutive bytes of host physical address 412 space this decoder claims at address N before the decode rotates 413 to the next target in the interleave at address N + 414 interleave_granularity (assuming N is aligned to 415 interleave_granularity). 416 417 418What: /sys/bus/cxl/devices/decoderX.Y/create_pmem_region 419What: /sys/bus/cxl/devices/decoderX.Y/create_ram_region 420Date: May, 2022, January, 2023 421KernelVersion: v6.0 (pmem), v6.3 (ram) 422Contact: linux-cxl@vger.kernel.org 423Description: 424 (RW) Write a string in the form 'regionZ' to start the process 425 of defining a new persistent, or volatile memory region 426 (interleave-set) within the decode range bounded by root decoder 427 'decoderX.Y'. The value written must match the current value 428 returned from reading this attribute. An atomic compare exchange 429 operation is done on write to assign the requested id to a 430 region and allocate the region-id for the next creation attempt. 431 EBUSY is returned if the region name written does not match the 432 current cached value. 433 434 435What: /sys/bus/cxl/devices/decoderX.Y/delete_region 436Date: May, 2022 437KernelVersion: v6.0 438Contact: linux-cxl@vger.kernel.org 439Description: 440 (WO) Write a string in the form 'regionZ' to delete that region, 441 provided it is currently idle / not bound to a driver. 442 443 444What: /sys/bus/cxl/devices/decoderX.Y/qos_class 445Date: May, 2023 446KernelVersion: v6.5 447Contact: linux-cxl@vger.kernel.org 448Description: 449 (RO) For CXL host platforms that support "QoS Telemetry" this 450 root-decoder-only attribute conveys a platform specific cookie 451 that identifies a QoS performance class for the CXL Window. 452 This class-id can be compared against a similar "qos_class" 453 published for each memory-type that an endpoint supports. While 454 it is not required that endpoints map their local memory-class 455 to a matching platform class, mismatches are not recommended and 456 there are platform specific side-effects that may result. 457 458 459What: /sys/bus/cxl/devices/regionZ/uuid 460Date: May, 2022 461KernelVersion: v6.0 462Contact: linux-cxl@vger.kernel.org 463Description: 464 (RW) Write a unique identifier for the region. This field must 465 be set for persistent regions and it must not conflict with the 466 UUID of another region. For volatile ram regions this 467 attribute is a read-only empty string. 468 469 470What: /sys/bus/cxl/devices/regionZ/interleave_granularity 471Date: May, 2022 472KernelVersion: v6.0 473Contact: linux-cxl@vger.kernel.org 474Description: 475 (RW) Set the number of consecutive bytes each device in the 476 interleave set will claim. The possible interleave granularity 477 values are determined by the CXL spec and the participating 478 devices. 479 480 481What: /sys/bus/cxl/devices/regionZ/interleave_ways 482Date: May, 2022 483KernelVersion: v6.0 484Contact: linux-cxl@vger.kernel.org 485Description: 486 (RW) Configures the number of devices participating in the 487 region is set by writing this value. Each device will provide 488 1/interleave_ways of storage for the region. 489 490 491What: /sys/bus/cxl/devices/regionZ/size 492Date: May, 2022 493KernelVersion: v6.0 494Contact: linux-cxl@vger.kernel.org 495Description: 496 (RW) System physical address space to be consumed by the region. 497 When written trigger the driver to allocate space out of the 498 parent root decoder's address space. When read the size of the 499 address space is reported and should match the span of the 500 region's resource attribute. Size shall be set after the 501 interleave configuration parameters. Once set it cannot be 502 changed, only freed by writing 0. The kernel makes no guarantees 503 that data is maintained over an address space freeing event, and 504 there is no guarantee that a free followed by an allocate 505 results in the same address being allocated. If extended linear 506 cache is present, the size indicates extended linear cache size 507 plus the CXL region size. 508 509 510What: /sys/bus/cxl/devices/regionZ/extended_linear_cache_size 511Date: October, 2025 512KernelVersion: v6.19 513Contact: linux-cxl@vger.kernel.org 514Description: 515 (RO) The size of extended linear cache, if there is an extended 516 linear cache. Otherwise the attribute will not be visible. 517 518 519What: /sys/bus/cxl/devices/regionZ/locked 520Date: Mar, 2026 521KernelVersion: v7.1 522Contact: linux-cxl@vger.kernel.org 523Description: 524 (RO) The CXL driver has the capability to lock a region based on 525 a BIOS or platform dependent configuration. Regions created as 526 locked are never permitted to be destroyed. Resets to participating 527 decoders will not result in a region destroy and will not free the 528 decoder resources. 529 530 531What: /sys/bus/cxl/devices/regionZ/mode 532Date: January, 2023 533KernelVersion: v6.3 534Contact: linux-cxl@vger.kernel.org 535Description: 536 (RO) The mode of a region is established at region creation time 537 and dictates the mode of the endpoint decoder that comprise the 538 region. For more details on the possible modes see 539 /sys/bus/cxl/devices/decoderX.Y/mode 540 541 542What: /sys/bus/cxl/devices/regionZ/resource 543Date: May, 2022 544KernelVersion: v6.0 545Contact: linux-cxl@vger.kernel.org 546Description: 547 (RO) A region is a contiguous partition of a CXL root decoder 548 address space. Region capacity is allocated by writing to the 549 size attribute, the resulting physical address space determined 550 by the driver is reflected here. It is therefore not useful to 551 read this before writing a value to the size attribute. 552 553 554What: /sys/bus/cxl/devices/regionZ/target[0..N] 555Date: May, 2022 556KernelVersion: v6.0 557Contact: linux-cxl@vger.kernel.org 558Description: 559 (RW) Write an endpoint decoder object name to 'targetX' where X 560 is the intended position of the endpoint device in the region 561 interleave and N is the 'interleave_ways' setting for the 562 region. ENXIO is returned if the write results in an impossible 563 to map decode scenario, like the endpoint is unreachable at that 564 position relative to the root decoder interleave. EBUSY is 565 returned if the position in the region is already occupied, or 566 if the region is not in a state to accept interleave 567 configuration changes. EINVAL is returned if the object name is 568 not an endpoint decoder. Once all positions have been 569 successfully written a final validation for decode conflicts is 570 performed before activating the region. 571 572 573What: /sys/bus/cxl/devices/regionZ/commit 574Date: May, 2022 575KernelVersion: v6.0 576Contact: linux-cxl@vger.kernel.org 577Description: 578 (RW) Write a boolean 'true' string value to this attribute to 579 trigger the region to transition from the software programmed 580 state to the actively decoding in hardware state. The commit 581 operation in addition to validating that the region is in proper 582 configured state, validates that the decoders are being 583 committed in spec mandated order (last committed decoder id + 584 1), and checks that the hardware accepts the commit request. 585 Reading this value indicates whether the region is committed or 586 not. 587 588 589What: /sys/bus/cxl/devices/memX/trigger_poison_list 590Date: April, 2023 591KernelVersion: v6.4 592Contact: linux-cxl@vger.kernel.org 593Description: 594 (WO) When a boolean 'true' is written to this attribute the 595 memdev driver retrieves the poison list from the device. The 596 list consists of addresses that are poisoned, or would result 597 in poison if accessed, and the source of the poison. This 598 attribute is only visible for devices supporting the 599 capability. The retrieved errors are logged as kernel 600 events when cxl_poison event tracing is enabled. 601 602 603What: /sys/bus/cxl/devices/regionZ/accessY/read_bandwidth 604 /sys/bus/cxl/devices/regionZ/accessY/write_bandwidth 605Date: Jan, 2024 606KernelVersion: v6.9 607Contact: linux-cxl@vger.kernel.org 608Description: 609 (RO) The aggregated read or write bandwidth of the region. The 610 number is the accumulated read or write bandwidth of all CXL memory 611 devices that contributes to the region in MB/s. It is 612 identical data that should appear in 613 /sys/devices/system/node/nodeX/accessY/initiators/read_bandwidth or 614 /sys/devices/system/node/nodeX/accessY/initiators/write_bandwidth. 615 See Documentation/ABI/stable/sysfs-devices-node. access0 provides 616 the number to the closest initiator and access1 provides the 617 number to the closest CPU. 618 619 620What: /sys/bus/cxl/devices/regionZ/accessY/read_latency 621 /sys/bus/cxl/devices/regionZ/accessY/write_latency 622Date: Jan, 2024 623KernelVersion: v6.9 624Contact: linux-cxl@vger.kernel.org 625Description: 626 (RO) The read or write latency of the region. The number is 627 the worst read or write latency of all CXL memory devices that 628 contributes to the region in nanoseconds. It is identical data 629 that should appear in 630 /sys/devices/system/node/nodeX/accessY/initiators/read_latency or 631 /sys/devices/system/node/nodeX/accessY/initiators/write_latency. 632 See Documentation/ABI/stable/sysfs-devices-node. access0 provides 633 the number to the closest initiator and access1 provides the 634 number to the closest CPU. 635 636 637What: /sys/bus/cxl/devices/nvdimm-bridge0/ndbusX/nmemY/cxl/dirty_shutdown 638Date: Feb, 2025 639KernelVersion: v6.15 640Contact: linux-cxl@vger.kernel.org 641Description: 642 (RO) The device dirty shutdown count value, which is the number 643 of times the device could have incurred in potential data loss. 644 The count is persistent across power loss and wraps back to 0 645 upon overflow. If this file is not present, the device does not 646 have the necessary support for dirty tracking. 647