1What: /sys/bus/coresight/devices/<tpdm-name>/integration_test 2Date: January 2023 3KernelVersion: 6.2 4Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 5Description: 6 (Write) Run integration test for tpdm. Integration test 7 will generate test data for tpdm. It can help to make 8 sure that the trace path is enabled and the link configurations 9 are fine. 10 11 Accepts only one of the 2 values - 1 or 2. 12 1 : Generate 64 bits data 13 2 : Generate 32 bits data 14 15What: /sys/bus/coresight/devices/<tpdm-name>/reset_dataset 16Date: March 2023 17KernelVersion: 6.7 18Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 19Description: 20 (Write) Reset the dataset of the tpdm. 21 22 Accepts only one value - 1. 23 1 : Reset the dataset of the tpdm 24 25What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_type 26Date: March 2023 27KernelVersion: 6.7 28Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 29Description: 30 (RW) Set/Get the trigger type of the DSB for tpdm. 31 32 Accepts only one of the 2 values - 0 or 1. 33 0 : Set the DSB trigger type to false 34 1 : Set the DSB trigger type to true 35 36What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_ts 37Date: March 2023 38KernelVersion: 6.7 39Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 40Description: 41 (RW) Set/Get the trigger timestamp of the DSB for tpdm. 42 43 Accepts only one of the 2 values - 0 or 1. 44 0 : Set the DSB trigger type to false 45 1 : Set the DSB trigger type to true 46 47What: /sys/bus/coresight/devices/<tpdm-name>/dsb_mode 48Date: March 2023 49KernelVersion: 6.7 50Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 51Description: 52 (RW) Set/Get the programming mode of the DSB for tpdm. 53 54 Accepts the value needs to be greater than 0. What data 55 bits do is listed below. 56 Bit[0:1] : Test mode control bit for choosing the inputs. 57 Bit[3] : Set to 0 for low performance mode. Set to 1 for high 58 performance mode. 59 Bit[4:8] : Select byte lane for high performance mode. 60 61What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_idx 62Date: March 2023 63KernelVersion: 6.7 64Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 65Description: 66 (RW) Set/Get the index number of the edge detection for the DSB 67 subunit TPDM. Since there are at most 256 edge detections, this 68 value ranges from 0 to 255. 69 70What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_val 71Date: March 2023 72KernelVersion: 6.7 73Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 74Description: 75 Write a data to control the edge detection corresponding to 76 the index number. Before writing data to this sysfs file, 77 "ctrl_idx" should be written first to configure the index 78 number of the edge detection which needs to be controlled. 79 80 Accepts only one of the following values. 81 0 - Rising edge detection 82 1 - Falling edge detection 83 2 - Rising and falling edge detection (toggle detection) 84 85 86What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_mask 87Date: March 2023 88KernelVersion: 6.7 89Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 90Description: 91 Write a data to mask the edge detection corresponding to the index 92 number. Before writing data to this sysfs file, "ctrl_idx" should 93 be written first to configure the index number of the edge detection 94 which needs to be masked. 95 96 Accepts only one of the 2 values - 0 or 1. 97 98What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcr[0:15] 99Date: March 2023 100KernelVersion: 6.7 101Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 102Description: 103 Read a set of the edge control value of the DSB in TPDM. 104 105What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcmr[0:7] 106Date: March 2023 107KernelVersion: 6.7 108Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 109Description: 110 Read a set of the edge control mask of the DSB in TPDM. 111 112What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpr[0:7] 113Date: March 2023 114KernelVersion: 6.7 115Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 116Description: 117 (RW) Set/Get the value of the trigger pattern for the DSB 118 subunit TPDM. 119 120What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpmr[0:7] 121Date: March 2023 122KernelVersion: 6.7 123Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 124Description: 125 (RW) Set/Get the mask of the trigger pattern for the DSB 126 subunit TPDM. 127 128What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpr[0:7] 129Date: March 2023 130KernelVersion: 6.7 131Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 132Description: 133 (RW) Set/Get the value of the pattern for the DSB subunit TPDM. 134 135What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpmr[0:7] 136Date: March 2023 137KernelVersion: 6.7 138Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 139Description: 140 (RW) Set/Get the mask of the pattern for the DSB subunit TPDM. 141 142What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/enable_ts 143Date: March 2023 144KernelVersion: 6.7 145Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 146Description: 147 (Write) Set the pattern timestamp of DSB tpdm. Read 148 the pattern timestamp of DSB tpdm. 149 150 Accepts only one of the 2 values - 0 or 1. 151 0 : Disable DSB pattern timestamp. 152 1 : Enable DSB pattern timestamp. 153 154What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/set_type 155Date: March 2023 156KernelVersion: 6.7 157Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 158Description: 159 (Write) Set the pattern type of DSB tpdm. Read 160 the pattern type of DSB tpdm. 161 162 Accepts only one of the 2 values - 0 or 1. 163 0 : Set the DSB pattern type to value. 164 1 : Set the DSB pattern type to toggle. 165 166What: /sys/bus/coresight/devices/<tpdm-name>/dsb_msr/msr[0:31] 167Date: March 2023 168KernelVersion: 6.7 169Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 170Description: 171 (RW) Set/Get the MSR(mux select register) for the DSB subunit 172 TPDM. 173 174What: /sys/bus/coresight/devices/<tpdm-name>/cmb_mode 175Date: January 2024 176KernelVersion: 6.9 177Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 178Description: (Write) Set the data collection mode of CMB tpdm. Continuous 179 change creates CMB data set elements on every CMBCLK edge. 180 Trace-on-change creates CMB data set elements only when a new 181 data set element differs in value from the previous element 182 in a CMB data set. 183 184 Accepts only one of the 2 values - 0 or 1. 185 0 : Continuous CMB collection mode. 186 1 : Trace-on-change CMB collection mode. 187 188What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_patt/xpr[0:1] 189Date: January 2024 190KernelVersion: 6.9 191Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 192Description: 193 (RW) Set/Get the value of the trigger pattern for the CMB 194 subunit TPDM. 195 196What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_patt/xpmr[0:1] 197Date: January 2024 198KernelVersion: 6.9 199Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 200Description: 201 (RW) Set/Get the mask of the trigger pattern for the CMB 202 subunit TPDM. 203 204What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpr[0:1] 205Date: January 2024 206KernelVersion: 6.9 207Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 208Description: 209 (RW) Set/Get the value of the pattern for the CMB subunit TPDM. 210 211What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpmr[0:1] 212Date: January 2024 213KernelVersion: 6.9 214Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 215Description: 216 (RW) Set/Get the mask of the pattern for the CMB subunit TPDM. 217 218What: /sys/bus/coresight/devices/<tpdm-name>/cmb_patt/enable_ts 219Date: January 2024 220KernelVersion: 6.9 221Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 222Description: 223 (Write) Set the pattern timestamp of CMB tpdm. Read 224 the pattern timestamp of CMB tpdm. 225 226 Accepts only one of the 2 values - 0 or 1. 227 0 : Disable CMB pattern timestamp. 228 1 : Enable CMB pattern timestamp. 229 230What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_ts 231Date: January 2024 232KernelVersion: 6.9 233Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 234Description: 235 (RW) Set/Get the trigger timestamp of the CMB for tpdm. 236 237 Accepts only one of the 2 values - 0 or 1. 238 0 : Set the CMB trigger type to false 239 1 : Set the CMB trigger type to true 240 241What: /sys/bus/coresight/devices/<tpdm-name>/cmb_ts_all 242Date: January 2024 243KernelVersion: 6.9 244Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 245Description: 246 (RW) Read or write the status of timestamp upon all interface. 247 Only value 0 and 1 can be written to this node. Set this node to 1 to request 248 timestamp to all trace packet. 249 Accepts only one of the 2 values - 0 or 1. 250 0 : Disable the timestamp of all trace packets. 251 1 : Enable the timestamp of all trace packets. 252 253What: /sys/bus/coresight/devices/<tpdm-name>/cmb_msr/msr[0:31] 254Date: January 2024 255KernelVersion: 6.9 256Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 257Description: 258 (RW) Set/Get the MSR(mux select register) for the CMB subunit 259 TPDM. 260 261What: /sys/bus/coresight/devices/<tpdm-name>/mcmb_trig_lane 262Date: Feb 2025 263KernelVersion 6.15 264Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 265Description: 266 (RW) Set/Get which lane participates in the output pattern 267 match cross trigger mechanism for the MCMB subunit TPDM. 268 269What: /sys/bus/coresight/devices/<tpdm-name>/mcmb_lanes_select 270Date: Feb 2025 271KernelVersion 6.15 272Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com> 273Description: 274 (RW) Set/Get the enablement of the individual lane. 275 276What: /sys/bus/coresight/devices/<tpdm-name>/label 277Date: Aug 2025 278KernelVersion 6.18 279Contact: Mao Jinlong <quic_jinlmao@quicinc.com> 280Description: (Read) Show hardware context information of device. 281 282What: /sys/bus/coresight/devices/<tpdm-name>/traceid 283Date: March 2026 284KernelVersion: 7.1 285Contact: Jie Gan <jie.gan@oss.qualcomm.com> 286Description: 287 (R) Show the trace ID that will appear in the trace stream 288 coming from this TPDM. The trace ID is inherited from the 289 connected TPDA device and is fixed for the lifetime of the 290 device. Returns -EINVAL if the device has not been enabled yet. 291