17a25ec8eSMathieu PoirierWhat: /sys/bus/coresight/devices/<memory_map>.etb/enable_sink 27a25ec8eSMathieu PoirierDate: November 2014 37a25ec8eSMathieu PoirierKernelVersion: 3.19 47a25ec8eSMathieu PoirierContact: Mathieu Poirier <mathieu.poirier@linaro.org> 57a25ec8eSMathieu PoirierDescription: (RW) Add/remove a sink from a trace path. There can be multiple 67a25ec8eSMathieu Poirier source for a single sink. 77a25ec8eSMathieu Poirier ex: echo 1 > /sys/bus/coresight/devices/20010000.etb/enable_sink 87a25ec8eSMathieu Poirier 97a25ec8eSMathieu PoirierWhat: /sys/bus/coresight/devices/<memory_map>.etb/trigger_cntr 107a25ec8eSMathieu PoirierDate: November 2014 117a25ec8eSMathieu PoirierKernelVersion: 3.19 127a25ec8eSMathieu PoirierContact: Mathieu Poirier <mathieu.poirier@linaro.org> 137a25ec8eSMathieu PoirierDescription: (RW) Disables write access to the Trace RAM by stopping the 147a25ec8eSMathieu Poirier formatter after a defined number of words have been stored 157a25ec8eSMathieu Poirier following the trigger event. The number of 32-bit words written 167a25ec8eSMathieu Poirier into the Trace RAM following the trigger event is equal to the 177a25ec8eSMathieu Poirier value stored in this register+1 (from ARM ETB-TRM). 18*ad352acbSMathieu Poirier 19*ad352acbSMathieu PoirierWhat: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rdp 20*ad352acbSMathieu PoirierDate: March 2016 21*ad352acbSMathieu PoirierKernelVersion: 4.7 22*ad352acbSMathieu PoirierContact: Mathieu Poirier <mathieu.poirier@linaro.org> 23*ad352acbSMathieu PoirierDescription: (R) Defines the depth, in words, of the trace RAM in powers of 24*ad352acbSMathieu Poirier 2. The value is read directly from HW register RDP, 0x004. 25*ad352acbSMathieu Poirier 26*ad352acbSMathieu PoirierWhat: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/sts 27*ad352acbSMathieu PoirierDate: March 2016 28*ad352acbSMathieu PoirierKernelVersion: 4.7 29*ad352acbSMathieu PoirierContact: Mathieu Poirier <mathieu.poirier@linaro.org> 30*ad352acbSMathieu PoirierDescription: (R) Shows the value held by the ETB status register. The value 31*ad352acbSMathieu Poirier is read directly from HW register STS, 0x00C. 32*ad352acbSMathieu Poirier 33*ad352acbSMathieu PoirierWhat: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rrp 34*ad352acbSMathieu PoirierDate: March 2016 35*ad352acbSMathieu PoirierKernelVersion: 4.7 36*ad352acbSMathieu PoirierContact: Mathieu Poirier <mathieu.poirier@linaro.org> 37*ad352acbSMathieu PoirierDescription: (R) Shows the value held by the ETB RAM Read Pointer register 38*ad352acbSMathieu Poirier that is used to read entries from the Trace RAM over the APB 39*ad352acbSMathieu Poirier interface. The value is read directly from HW register RRP, 40*ad352acbSMathieu Poirier 0x014. 41*ad352acbSMathieu Poirier 42*ad352acbSMathieu PoirierWhat: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rwp 43*ad352acbSMathieu PoirierDate: March 2016 44*ad352acbSMathieu PoirierKernelVersion: 4.7 45*ad352acbSMathieu PoirierContact: Mathieu Poirier <mathieu.poirier@linaro.org> 46*ad352acbSMathieu PoirierDescription: (R) Shows the value held by the ETB RAM Write Pointer register 47*ad352acbSMathieu Poirier that is used to sets the write pointer to write entries from 48*ad352acbSMathieu Poirier the CoreSight bus into the Trace RAM. The value is read directly 49*ad352acbSMathieu Poirier from HW register RWP, 0x018. 50*ad352acbSMathieu Poirier 51*ad352acbSMathieu PoirierWhat: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/trg 52*ad352acbSMathieu PoirierDate: March 2016 53*ad352acbSMathieu PoirierKernelVersion: 4.7 54*ad352acbSMathieu PoirierContact: Mathieu Poirier <mathieu.poirier@linaro.org> 55*ad352acbSMathieu PoirierDescription: (R) Similar to "trigger_cntr" above except that this value is 56*ad352acbSMathieu Poirier read directly from HW register TRG, 0x01C. 57*ad352acbSMathieu Poirier 58*ad352acbSMathieu PoirierWhat: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ctl 59*ad352acbSMathieu PoirierDate: March 2016 60*ad352acbSMathieu PoirierKernelVersion: 4.7 61*ad352acbSMathieu PoirierContact: Mathieu Poirier <mathieu.poirier@linaro.org> 62*ad352acbSMathieu PoirierDescription: (R) Shows the value held by the ETB Control register. The value 63*ad352acbSMathieu Poirier is read directly from HW register CTL, 0x020. 64*ad352acbSMathieu Poirier 65*ad352acbSMathieu PoirierWhat: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffsr 66*ad352acbSMathieu PoirierDate: March 2016 67*ad352acbSMathieu PoirierKernelVersion: 4.7 68*ad352acbSMathieu PoirierContact: Mathieu Poirier <mathieu.poirier@linaro.org> 69*ad352acbSMathieu PoirierDescription: (R) Shows the value held by the ETB Formatter and Flush Status 70*ad352acbSMathieu Poirier register. The value is read directly from HW register FFSR, 71*ad352acbSMathieu Poirier 0x300. 72*ad352acbSMathieu Poirier 73*ad352acbSMathieu PoirierWhat: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffcr 74*ad352acbSMathieu PoirierDate: March 2016 75*ad352acbSMathieu PoirierKernelVersion: 4.7 76*ad352acbSMathieu PoirierContact: Mathieu Poirier <mathieu.poirier@linaro.org> 77*ad352acbSMathieu PoirierDescription: (R) Shows the value held by the ETB Formatter and Flush Control 78*ad352acbSMathieu Poirier register. The value is read directly from HW register FFCR, 79*ad352acbSMathieu Poirier 0x304. 80