1*7a25ec8eSMathieu PoirierWhat: /sys/bus/coresight/devices/<memory_map>.etb/enable_sink 2*7a25ec8eSMathieu PoirierDate: November 2014 3*7a25ec8eSMathieu PoirierKernelVersion: 3.19 4*7a25ec8eSMathieu PoirierContact: Mathieu Poirier <mathieu.poirier@linaro.org> 5*7a25ec8eSMathieu PoirierDescription: (RW) Add/remove a sink from a trace path. There can be multiple 6*7a25ec8eSMathieu Poirier source for a single sink. 7*7a25ec8eSMathieu Poirier ex: echo 1 > /sys/bus/coresight/devices/20010000.etb/enable_sink 8*7a25ec8eSMathieu Poirier 9*7a25ec8eSMathieu PoirierWhat: /sys/bus/coresight/devices/<memory_map>.etb/status 10*7a25ec8eSMathieu PoirierDate: November 2014 11*7a25ec8eSMathieu PoirierKernelVersion: 3.19 12*7a25ec8eSMathieu PoirierContact: Mathieu Poirier <mathieu.poirier@linaro.org> 13*7a25ec8eSMathieu PoirierDescription: (R) List various control and status registers. The specific 14*7a25ec8eSMathieu Poirier layout and content is driver specific. 15*7a25ec8eSMathieu Poirier 16*7a25ec8eSMathieu PoirierWhat: /sys/bus/coresight/devices/<memory_map>.etb/trigger_cntr 17*7a25ec8eSMathieu PoirierDate: November 2014 18*7a25ec8eSMathieu PoirierKernelVersion: 3.19 19*7a25ec8eSMathieu PoirierContact: Mathieu Poirier <mathieu.poirier@linaro.org> 20*7a25ec8eSMathieu PoirierDescription: (RW) Disables write access to the Trace RAM by stopping the 21*7a25ec8eSMathieu Poirier formatter after a defined number of words have been stored 22*7a25ec8eSMathieu Poirier following the trigger event. The number of 32-bit words written 23*7a25ec8eSMathieu Poirier into the Trace RAM following the trigger event is equal to the 24*7a25ec8eSMathieu Poirier value stored in this register+1 (from ARM ETB-TRM). 25