17a25ec8eSMathieu PoirierWhat: /sys/bus/coresight/devices/<memory_map>.etb/enable_sink 27a25ec8eSMathieu PoirierDate: November 2014 37a25ec8eSMathieu PoirierKernelVersion: 3.19 47a25ec8eSMathieu PoirierContact: Mathieu Poirier <mathieu.poirier@linaro.org> 57a25ec8eSMathieu PoirierDescription: (RW) Add/remove a sink from a trace path. There can be multiple 67a25ec8eSMathieu Poirier source for a single sink. 7*54a19b4dSMauro Carvalho Chehab 8*54a19b4dSMauro Carvalho Chehab ex:: 9*54a19b4dSMauro Carvalho Chehab 10*54a19b4dSMauro Carvalho Chehab echo 1 > /sys/bus/coresight/devices/20010000.etb/enable_sink 117a25ec8eSMathieu Poirier 127a25ec8eSMathieu PoirierWhat: /sys/bus/coresight/devices/<memory_map>.etb/trigger_cntr 137a25ec8eSMathieu PoirierDate: November 2014 147a25ec8eSMathieu PoirierKernelVersion: 3.19 157a25ec8eSMathieu PoirierContact: Mathieu Poirier <mathieu.poirier@linaro.org> 167a25ec8eSMathieu PoirierDescription: (RW) Disables write access to the Trace RAM by stopping the 177a25ec8eSMathieu Poirier formatter after a defined number of words have been stored 187a25ec8eSMathieu Poirier following the trigger event. The number of 32-bit words written 197a25ec8eSMathieu Poirier into the Trace RAM following the trigger event is equal to the 207a25ec8eSMathieu Poirier value stored in this register+1 (from ARM ETB-TRM). 21ad352acbSMathieu Poirier 22ad352acbSMathieu PoirierWhat: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rdp 23ad352acbSMathieu PoirierDate: March 2016 24ad352acbSMathieu PoirierKernelVersion: 4.7 25ad352acbSMathieu PoirierContact: Mathieu Poirier <mathieu.poirier@linaro.org> 26ad352acbSMathieu PoirierDescription: (R) Defines the depth, in words, of the trace RAM in powers of 27ad352acbSMathieu Poirier 2. The value is read directly from HW register RDP, 0x004. 28ad352acbSMathieu Poirier 29ad352acbSMathieu PoirierWhat: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/sts 30ad352acbSMathieu PoirierDate: March 2016 31ad352acbSMathieu PoirierKernelVersion: 4.7 32ad352acbSMathieu PoirierContact: Mathieu Poirier <mathieu.poirier@linaro.org> 33ad352acbSMathieu PoirierDescription: (R) Shows the value held by the ETB status register. The value 34ad352acbSMathieu Poirier is read directly from HW register STS, 0x00C. 35ad352acbSMathieu Poirier 36ad352acbSMathieu PoirierWhat: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rrp 37ad352acbSMathieu PoirierDate: March 2016 38ad352acbSMathieu PoirierKernelVersion: 4.7 39ad352acbSMathieu PoirierContact: Mathieu Poirier <mathieu.poirier@linaro.org> 40ad352acbSMathieu PoirierDescription: (R) Shows the value held by the ETB RAM Read Pointer register 41ad352acbSMathieu Poirier that is used to read entries from the Trace RAM over the APB 42ad352acbSMathieu Poirier interface. The value is read directly from HW register RRP, 43ad352acbSMathieu Poirier 0x014. 44ad352acbSMathieu Poirier 45ad352acbSMathieu PoirierWhat: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rwp 46ad352acbSMathieu PoirierDate: March 2016 47ad352acbSMathieu PoirierKernelVersion: 4.7 48ad352acbSMathieu PoirierContact: Mathieu Poirier <mathieu.poirier@linaro.org> 49ad352acbSMathieu PoirierDescription: (R) Shows the value held by the ETB RAM Write Pointer register 50ad352acbSMathieu Poirier that is used to sets the write pointer to write entries from 51ad352acbSMathieu Poirier the CoreSight bus into the Trace RAM. The value is read directly 52ad352acbSMathieu Poirier from HW register RWP, 0x018. 53ad352acbSMathieu Poirier 54ad352acbSMathieu PoirierWhat: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/trg 55ad352acbSMathieu PoirierDate: March 2016 56ad352acbSMathieu PoirierKernelVersion: 4.7 57ad352acbSMathieu PoirierContact: Mathieu Poirier <mathieu.poirier@linaro.org> 58ad352acbSMathieu PoirierDescription: (R) Similar to "trigger_cntr" above except that this value is 59ad352acbSMathieu Poirier read directly from HW register TRG, 0x01C. 60ad352acbSMathieu Poirier 61ad352acbSMathieu PoirierWhat: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ctl 62ad352acbSMathieu PoirierDate: March 2016 63ad352acbSMathieu PoirierKernelVersion: 4.7 64ad352acbSMathieu PoirierContact: Mathieu Poirier <mathieu.poirier@linaro.org> 65ad352acbSMathieu PoirierDescription: (R) Shows the value held by the ETB Control register. The value 66ad352acbSMathieu Poirier is read directly from HW register CTL, 0x020. 67ad352acbSMathieu Poirier 68ad352acbSMathieu PoirierWhat: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffsr 69ad352acbSMathieu PoirierDate: March 2016 70ad352acbSMathieu PoirierKernelVersion: 4.7 71ad352acbSMathieu PoirierContact: Mathieu Poirier <mathieu.poirier@linaro.org> 72ad352acbSMathieu PoirierDescription: (R) Shows the value held by the ETB Formatter and Flush Status 73ad352acbSMathieu Poirier register. The value is read directly from HW register FFSR, 74ad352acbSMathieu Poirier 0x300. 75ad352acbSMathieu Poirier 76ad352acbSMathieu PoirierWhat: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffcr 77ad352acbSMathieu PoirierDate: March 2016 78ad352acbSMathieu PoirierKernelVersion: 4.7 79ad352acbSMathieu PoirierContact: Mathieu Poirier <mathieu.poirier@linaro.org> 80ad352acbSMathieu PoirierDescription: (R) Shows the value held by the ETB Formatter and Flush Control 81ad352acbSMathieu Poirier register. The value is read directly from HW register FFCR, 82ad352acbSMathieu Poirier 0x304. 83