1 /*- 2 * Copyright (c) 2018-2020 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33 #ifndef _ARM64_CORESIGHT_CORESIGHT_H_ 34 #define _ARM64_CORESIGHT_CORESIGHT_H_ 35 36 #include "opt_acpi.h" 37 #include "opt_platform.h" 38 39 #include <sys/bus.h> 40 41 #ifdef FDT 42 #include <dev/ofw/openfirm.h> 43 #endif 44 45 #ifdef DEV_ACPI 46 #include <contrib/dev/acpica/include/acpi.h> 47 #include <dev/acpica/acpivar.h> 48 #endif 49 50 #define CORESIGHT_ITCTRL 0xf00 51 #define CORESIGHT_CLAIMSET 0xfa0 52 #define CORESIGHT_CLAIMCLR 0xfa4 53 #define CORESIGHT_LAR 0xfb0 54 #define CORESIGHT_UNLOCK 0xc5acce55 55 #define CORESIGHT_LSR 0xfb4 56 #define CORESIGHT_AUTHSTATUS 0xfb8 57 #define CORESIGHT_DEVID 0xfc8 58 #define CORESIGHT_DEVTYPE 0xfcc 59 60 enum cs_dev_type { 61 CORESIGHT_ETMV4, 62 CORESIGHT_TMC, 63 CORESIGHT_DYNAMIC_REPLICATOR, 64 CORESIGHT_FUNNEL, 65 CORESIGHT_CPU_DEBUG, 66 }; 67 68 enum cs_bus_type { 69 CORESIGHT_BUS_ACPI, 70 CORESIGHT_BUS_FDT, 71 }; 72 73 struct coresight_device { 74 TAILQ_ENTRY(coresight_device) link; 75 device_t dev; 76 enum cs_dev_type dev_type; 77 struct coresight_platform_data *pdata; 78 }; 79 80 struct endpoint { 81 TAILQ_ENTRY(endpoint) link; 82 #ifdef FDT 83 phandle_t my_node; 84 phandle_t their_node; 85 phandle_t dev_node; 86 #endif 87 #ifdef DEV_ACPI 88 ACPI_HANDLE their_handle; 89 ACPI_HANDLE my_handle; 90 #endif 91 boolean_t input; 92 int reg; 93 struct coresight_device *cs_dev; 94 LIST_ENTRY(endpoint) endplink; 95 }; 96 97 struct coresight_platform_data { 98 int cpu; 99 int in_ports; 100 int out_ports; 101 struct mtx mtx_lock; 102 TAILQ_HEAD(endpoint_list, endpoint) endpoints; 103 enum cs_bus_type bus_type; 104 }; 105 106 struct coresight_desc { 107 struct coresight_platform_data *pdata; 108 device_t dev; 109 enum cs_dev_type dev_type; 110 }; 111 112 TAILQ_HEAD(coresight_device_list, coresight_device); 113 114 #define ETM_N_COMPRATOR 16 115 116 struct etm_state { 117 uint32_t trace_id; 118 }; 119 120 struct etr_state { 121 boolean_t started; 122 uint32_t cycle; 123 uint32_t offset; 124 uint32_t low; 125 uint32_t high; 126 uint32_t bufsize; 127 uint32_t flags; 128 #define ETR_FLAG_ALLOCATE (1 << 0) 129 #define ETR_FLAG_RELEASE (1 << 1) 130 }; 131 132 struct coresight_event { 133 LIST_HEAD(, endpoint) endplist; 134 135 uint64_t addr[ETM_N_COMPRATOR]; 136 uint32_t naddr; 137 uint8_t excp_level; 138 enum cs_dev_type src; 139 enum cs_dev_type sink; 140 141 struct etr_state etr; 142 struct etm_state etm; 143 }; 144 145 struct etm_config { 146 uint64_t addr[ETM_N_COMPRATOR]; 147 uint32_t naddr; 148 uint8_t excp_level; 149 }; 150 151 static MALLOC_DEFINE(M_CORESIGHT, "coresight", "ARM Coresight"); 152 153 struct coresight_platform_data *coresight_fdt_get_platform_data(device_t dev); 154 struct coresight_platform_data *coresight_acpi_get_platform_data(device_t dev); 155 struct endpoint * coresight_get_output_endpoint(struct coresight_platform_data *pdata); 156 struct coresight_device * coresight_get_output_device(struct endpoint *endp, struct endpoint **); 157 int coresight_register(struct coresight_desc *desc); 158 int coresight_init_event(int cpu, struct coresight_event *event); 159 void coresight_enable(int cpu, struct coresight_event *event); 160 void coresight_disable(int cpu, struct coresight_event *event); 161 void coresight_read(int cpu, struct coresight_event *event); 162 163 #endif /* !_ARM64_CORESIGHT_CORESIGHT_H_ */ 164