| /linux/drivers/net/wireless/realtek/rtw88/ |
| H A D | fw.h | 400 #define SET_PKT_H2C_CATEGORY(h2c_pkt, value) \ argument
401 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(6, 0))
402 #define SET_PKT_H2C_CMD_ID(h2c_pkt, value) \ argument
403 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
404 #define SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, value) \ argument
405 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 16))
406 #define SET_PKT_H2C_TOTAL_LEN(h2c_pkt, value) \ argument
407 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 0))
416 #define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \ argument
417 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 16))
[all …]
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| /linux/drivers/media/pci/cx25821/ |
| H A D | cx25821-medusa-video.c | 24 u32 value = 0; in medusa_enable_bluefield_output() local
63 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp); in medusa_enable_bluefield_output()
64 value &= 0xFFFFFF7F; /* clear BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
66 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
67 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value); in medusa_enable_bluefield_output()
69 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp); in medusa_enable_bluefield_output()
70 value &= 0xFFFFFF7F; in medusa_enable_bluefield_output()
72 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
73 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value); in medusa_enable_bluefield_output()
80 u32 value = 0; in medusa_initialize_ntsc() local
[all …]
|
| /linux/tools/testing/selftests/kvm/include/x86/ |
| H A D | evmcs.h | 268 static inline int evmcs_vmptrst(u64 *value) in evmcs_vmptrst() argument
270 *value = current_vp_assist->current_nested_vmcs & in evmcs_vmptrst()
276 static inline int evmcs_vmread(u64 encoding, u64 *value) in evmcs_vmread() argument
280 *value = current_evmcs->guest_rip; in evmcs_vmread()
283 *value = current_evmcs->guest_rsp; in evmcs_vmread()
286 *value = current_evmcs->guest_rflags; in evmcs_vmread()
289 *value = current_evmcs->host_ia32_pat; in evmcs_vmread()
292 *value = current_evmcs->host_ia32_efer; in evmcs_vmread()
295 *value = current_evmcs->host_cr0; in evmcs_vmread()
298 *value = current_evmcs->host_cr3; in evmcs_vmread()
[all …]
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| /linux/drivers/phy/tegra/ |
| H A D | xusb-tegra210.c | 468 u32 value; in tegra210_pex_uphy_enable() local
486 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
487 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK << in tegra210_pex_uphy_enable()
489 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL << in tegra210_pex_uphy_enable()
491 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
493 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
494 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK << in tegra210_pex_uphy_enable()
496 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL << in tegra210_pex_uphy_enable()
498 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
500 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
[all …]
|
| H A D | xusb-tegra186.c | 281 static inline void ao_writel(struct tegra186_xusb_padctl *priv, u32 value, unsigned int offset) in ao_writel() argument
283 writel(value, priv->ao_regs + offset); in ao_writel()
337 u32 value; in tegra186_utmi_enable_phy_sleepwalk() local
342 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
343 value &= ~MASTER_ENABLE; in tegra186_utmi_enable_phy_sleepwalk()
344 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
347 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
348 value |= MASTER_CFG_SEL; in tegra186_utmi_enable_phy_sleepwalk()
349 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
352 value = ao_readl(priv, XUSB_AO_USB_DEBOUNCE_DEL); in tegra186_utmi_enable_phy_sleepwalk()
[all …]
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| H A D | xusb-tegra124.c | 227 u32 value; in tegra124_xusb_padctl_enable() local
234 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
235 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; in tegra124_xusb_padctl_enable()
236 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
240 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
241 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; in tegra124_xusb_padctl_enable()
242 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
246 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
247 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; in tegra124_xusb_padctl_enable()
248 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
[all …]
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| /linux/drivers/video/fbdev/riva/ |
| H A D | nvreg.h | 34 #define SetBF(mask,value) ((value) << (0?mask)) argument
37 #define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \ argument
38 | SetBF(mask,value)))
47 #define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) argument
51 #define DEVICE_DEF(device,mask,value) \ argument
52 SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value)
53 #define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value) argument
56 #define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value) argument
59 #define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value) argument
60 #define PDAC_Val(mask,value) DEVICE_VALUE(PDAC,mask,value) argument
[all …]
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| /linux/tools/perf/util/annotate-arch/ |
| H A D | annotate-powerpc.c | 146 int value; member
168 { .name = "OP_31_XOP_LXSIWZX", .value = 12, },
169 { .name = "OP_31_XOP_LWARX", .value = 20, },
170 { .name = "OP_31_XOP_LDX", .value = 21, },
171 { .name = "OP_31_XOP_LWZX", .value = 23, },
172 { .name = "OP_31_XOP_LDUX", .value = 53, },
173 { .name = "OP_31_XOP_LWZUX", .value = 55, },
174 { .name = "OP_31_XOP_LXSIWAX", .value = 76, },
175 { .name = "OP_31_XOP_LDARX", .value = 84, },
176 { .name = "OP_31_XOP_LBZX", .value = 87, },
[all …]
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| /linux/tools/power/x86/intel-speed-select/ |
| H A D | isst-display.c | 85 char *value) in format_and_print_txt() argument
102 if (header && value) { in format_and_print_txt()
104 fprintf(outf, "%s:%s\n", header, value); in format_and_print_txt()
112 static void format_and_print(FILE *outf, int level, char *header, char *value) in format_and_print() argument
119 format_and_print_txt(outf, level, header, value); in format_and_print()
139 if (value) { in format_and_print()
144 fprintf(outf, "\"%s\"", value); in format_and_print()
222 static char value[1024]; in _isst_pbf_display_information() local
228 snprintf(value, sizeof(value), "%d", in _isst_pbf_display_information()
230 format_and_print(outf, disp_level + 1, header, value); in _isst_pbf_display_information()
[all …]
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| /linux/drivers/gpu/drm/amd/display/include/ |
| H A D | fixed31_32.h | 58 long long value; member
91 res.value = (long long) arg << FIXED31_32_BITS_PER_FRACTIONAL_PART; in dc_fixpt_from_int()
109 res.value = -arg.value; in dc_fixpt_neg()
120 if (arg.value < 0) in dc_fixpt_abs()
137 return arg1.value < arg2.value; in dc_fixpt_lt()
146 return arg1.value <= arg2.value; in dc_fixpt_le()
155 return arg1.value == arg2.value; in dc_fixpt_eq()
164 if (arg1.value <= arg2.value) in dc_fixpt_min()
176 if (arg1.value <= arg2.value) in dc_fixpt_max()
212 ASSERT(((arg.value >= 0) && (arg.value <= LLONG_MAX >> shift)) || in dc_fixpt_shl()
[all …]
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| /linux/tools/testing/selftests/bpf/test_kmods/ |
| H A D | bpf_testmod.h | 28 /* BPF iter that returns *value* *n* times in a row */
30 s64 value;
60 int (*tramp_1)(int value);
61 int (*tramp_2)(int value);
62 int (*tramp_3)(int value);
63 int (*tramp_4)(int value);
64 int (*tramp_5)(int value);
65 int (*tramp_6)(int value);
66 int (*tramp_7)(int value);
67 int (*tramp_8)(int value);
29 s64 value; global() member
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_scl_filters.c | 1343 if (ratio.value < dc_fixpt_one.value) in get_filter_3tap_16p()
1345 else if (ratio.value < dc_fixpt_from_fraction(4, 3).value) in get_filter_3tap_16p()
1347 else if (ratio.value < dc_fixpt_from_fraction(5, 3).value) in get_filter_3tap_16p()
1355 if (ratio.value < dc_fixpt_one.value) in get_filter_3tap_64p()
1357 else if (ratio.value < dc_fixpt_from_fraction(4, 3).value) in get_filter_3tap_64p()
1359 else if (ratio.value < dc_fixpt_from_fraction(5, 3).value) in get_filter_3tap_64p()
1367 if (ratio.value < dc_fixpt_one.value) in get_filter_4tap_16p()
1369 else if (ratio.value < dc_fixpt_from_fraction(4, 3).value) in get_filter_4tap_16p()
1371 else if (ratio.value < dc_fixpt_from_fraction(5, 3).value) in get_filter_4tap_16p()
1379 if (ratio.value < dc_fixpt_one.value) in get_filter_4tap_64p()
[all …]
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| /linux/drivers/net/ethernet/stmicro/stmmac/ |
| H A D | stmmac_vlan.c | 168 u32 value; in vlan_update_hash() local
172 value = readl(ioaddr + VLAN_TAG); in vlan_update_hash()
175 value |= VLAN_VTHM | VLAN_ETV; in vlan_update_hash()
177 value |= VLAN_EDVLP; in vlan_update_hash()
178 value |= VLAN_ESVL; in vlan_update_hash()
179 value |= VLAN_DOVLTC; in vlan_update_hash()
181 value &= ~VLAN_EDVLP; in vlan_update_hash()
182 value &= ~VLAN_ESVL; in vlan_update_hash()
183 value &= ~VLAN_DOVLTC; in vlan_update_hash()
186 writel(value, ioaddr + VLAN_TAG); in vlan_update_hash()
[all …]
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| /linux/drivers/net/wwan/t7xx/ |
| H A D | t7xx_dpmaif.c | 37 u32 value, ul_intr_enable, dl_intr_enable; in t7xx_dpmaif_init_intr() local
50 value, (value & ul_intr_enable) != ul_intr_enable, 0, in t7xx_dpmaif_init_intr()
65 value, (value & ul_intr_enable) != ul_intr_enable, 0, in t7xx_dpmaif_init_intr()
74 value = ioread32(hw_info->pcie_base + DPMAIF_AO_UL_AP_L1TIMR0); in t7xx_dpmaif_init_intr()
75 value |= DPMAIF_DL_INT_Q2APTOP | DPMAIF_DL_INT_Q2TOQ1; in t7xx_dpmaif_init_intr()
76 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_UL_AP_L1TIMR0); in t7xx_dpmaif_init_intr()
85 u32 value, ul_int_que_done; in t7xx_dpmaif_mask_ulq_intr() local
94 value, (value & ul_int_que_done) == ul_int_que_done, 0, in t7xx_dpmaif_mask_ulq_intr()
99 value); in t7xx_dpmaif_mask_ulq_intr()
105 u32 value, ul_int_que_done; in t7xx_dpmaif_unmask_ulq_intr() local
[all …]
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| /linux/arch/mips/include/asm/ |
| H A D | unaligned-emul.h | 8 #define _LoadHW(addr, value, res, type) \ argument
26 : "=&r" (value), "=r" (res) \
31 #define _LoadW(addr, value, res, type) \ argument
47 : "=&r" (value), "=r" (res) \
53 #define _LoadW(addr, value, res, type) \ argument
82 : "=&r" (value), "=r" (res) \
88 #define _LoadHWU(addr, value, res, type) \ argument
108 : "=&r" (value), "=r" (res) \
113 #define _LoadWU(addr, value, res, type) \ argument
131 : "=&r" (value), "=r" (res) \
[all …]
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| /linux/arch/mips/include/asm/octeon/ |
| H A D | cvmx-fau.h | 62 int64_t value:63; member
72 int32_t value:31; member
82 int16_t value:15; member
92 int8_t value:7; member
153 int64_t value) in __cvmx_fau_atomic_address() argument
156 cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) | in __cvmx_fau_atomic_address()
171 int64_t value) in cvmx_fau_fetch_and_add64() argument
173 return cvmx_read64_int64(__cvmx_fau_atomic_address(0, reg, value)); in cvmx_fau_fetch_and_add64()
186 int32_t value) in cvmx_fau_fetch_and_add32() argument
189 return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value)); in cvmx_fau_fetch_and_add32()
[all …]
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| /linux/sound/soc/ti/ |
| H A D | omap-mcbsp-priv.h | 78 #define RINTM(value) (((value) & 0x3) << 4) /* bits 4:5 */ argument
81 #define CLKSTP(value) (((value) & 0x3) << 11) /* bits 11:12 */ argument
82 #define RJUST(value) (((value) & 0x3) << 13) /* bits 13:14 */ argument
91 #define XINTM(value) (((value) & 0x3) << 4) /* bits 4:5 */ argument
115 #define RWDLEN1(value) (((value) & 0x7) << 5) /* Bits 5:7 */ argument
116 #define RFRLEN1(value) (((value) & 0x7f) << 8) /* Bits 8:14 */ argument
119 #define XWDLEN1(value) (((value) & 0x7) << 5) /* Bits 5:7 */ argument
120 #define XFRLEN1(value) (((value) & 0x7f) << 8) /* Bits 8:14 */ argument
123 #define RDATDLY(value) ((value) & 0x3) /* Bits 0:1 */ argument
125 #define RCOMPAND(value) (((value) & 0x3) << 3) /* Bits 3:4 */ argument
[all …]
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| /linux/drivers/gpu/drm/tegra/ |
| H A D | sor.c | 489 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl() local
491 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
493 return value; in tegra_sor_readl()
496 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() argument
499 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
500 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
547 u32 value; in tegra_clk_sor_pad_set_parent() local
549 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
550 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_clk_sor_pad_set_parent()
554 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; in tegra_clk_sor_pad_set_parent()
[all …]
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| /linux/include/acpi/ |
| H A D | acbuffer.h | 122 #define ACPI_PLD_SET_REVISION(dword,value) ACPI_SET_BITS (dword, 0, ACPI_7BIT_MASK, value) /* … argument
125 #define ACPI_PLD_SET_IGNORE_COLOR(dword,value) ACPI_SET_BITS (dword, 7, ACPI_1BIT_MASK, value) /* … argument
128 #define ACPI_PLD_SET_RED(dword,value) ACPI_SET_BITS (dword, 8, ACPI_8BIT_MASK, value) /* … argument
131 #define ACPI_PLD_SET_GREEN(dword,value) ACPI_SET_BITS (dword, 16, ACPI_8BIT_MASK, value) /*… argument
134 #define ACPI_PLD_SET_BLUE(dword,value) ACPI_SET_BITS (dword, 24, ACPI_8BIT_MASK, value) /*… argument
139 #define ACPI_PLD_SET_WIDTH(dword,value) ACPI_SET_BITS (dword, 0, ACPI_16BIT_MASK, value) /*… argument
142 #define ACPI_PLD_SET_HEIGHT(dword,value) ACPI_SET_BITS (dword, 16, ACPI_16BIT_MASK, value) /… argument
147 #define ACPI_PLD_SET_USER_VISIBLE(dword,value) ACPI_SET_BITS (dword, 0, ACPI_1BIT_MASK, value) /* … argument
150 #define ACPI_PLD_SET_DOCK(dword,value) ACPI_SET_BITS (dword, 1, ACPI_1BIT_MASK, value) /* … argument
153 #define ACPI_PLD_SET_LID(dword,value) ACPI_SET_BITS (dword, 2, ACPI_1BIT_MASK, value) /* … argument
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | bw_fixed.h | 33 int64_t value; member
45 return (arg1.value <= arg2.value) ? arg1 : arg2; in bw_min2()
51 return (arg2.value <= arg1.value) ? arg1 : arg2; in bw_max2()
68 struct bw_fixed bw_int_to_fixed_nonconst(int64_t value);
69 static inline struct bw_fixed bw_int_to_fixed(int64_t value) in bw_int_to_fixed() argument
71 if (__builtin_constant_p(value)) { in bw_int_to_fixed()
73 BUILD_BUG_ON(value > BW_FIXED_MAX_I32 || value < BW_FIXED_MIN_I32); in bw_int_to_fixed()
74 res.value = value << BW_FIXED_BITS_PER_FRACTIONAL_PART; in bw_int_to_fixed()
77 return bw_int_to_fixed_nonconst(value); in bw_int_to_fixed()
80 static inline int32_t bw_fixed_to_int(struct bw_fixed value) in bw_fixed_to_int() argument
[all …]
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| /linux/drivers/net/ethernet/sfc/siena/ |
| H A D | io.h | 84 static inline void _efx_writeq(struct efx_nic *efx, __le64 value, in _efx_writeq() argument
87 __raw_writeq((__force u64)value, efx->membase + reg); in _efx_writeq()
95 static inline void _efx_writed(struct efx_nic *efx, __le32 value, in _efx_writed() argument
98 __raw_writel((__force u32)value, efx->membase + reg); in _efx_writed()
106 static inline void efx_writeo(struct efx_nic *efx, const efx_oword_t *value, in efx_writeo() argument
113 EFX_OWORD_VAL(*value)); in efx_writeo()
117 _efx_writeq(efx, value->u64[0], reg + 0); in efx_writeo()
118 _efx_writeq(efx, value->u64[1], reg + 8); in efx_writeo()
120 _efx_writed(efx, value->u32[0], reg + 0); in efx_writeo()
121 _efx_writed(efx, value->u32[1], reg + 4); in efx_writeo()
[all …]
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| /linux/drivers/net/ethernet/sfc/falcon/ |
| H A D | io.h | 67 static inline void _ef4_writeq(struct ef4_nic *efx, __le64 value, in _ef4_writeq() argument
70 __raw_writeq((__force u64)value, efx->membase + reg); in _ef4_writeq()
78 static inline void _ef4_writed(struct ef4_nic *efx, __le32 value, in _ef4_writed() argument
81 __raw_writel((__force u32)value, efx->membase + reg); in _ef4_writed()
89 static inline void ef4_writeo(struct ef4_nic *efx, const ef4_oword_t *value, in ef4_writeo() argument
96 EF4_OWORD_VAL(*value)); in ef4_writeo()
100 _ef4_writeq(efx, value->u64[0], reg + 0); in ef4_writeo()
101 _ef4_writeq(efx, value->u64[1], reg + 8); in ef4_writeo()
103 _ef4_writed(efx, value->u32[0], reg + 0); in ef4_writeo()
104 _ef4_writed(efx, value->u32[1], reg + 4); in ef4_writeo()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/basics/ |
| H A D | bw_fixed.c | 49 struct bw_fixed bw_int_to_fixed_nonconst(int64_t value) in bw_int_to_fixed_nonconst() argument
53 ASSERT(value < BW_FIXED_MAX_I32 && value > BW_FIXED_MIN_I32); in bw_int_to_fixed_nonconst()
54 res.value = value << BW_FIXED_BITS_PER_FRACTIONAL_PART; in bw_int_to_fixed_nonconst()
103 res.value = (int64_t)(res_value); in bw_frc_to_fixed()
106 res.value = -res.value; in bw_frc_to_fixed()
116 multiplicand = div64_s64(arg.value, abs_i64(significance.value)); in bw_floor2()
117 result.value = abs_i64(significance.value) * multiplicand; in bw_floor2()
118 ASSERT(abs_i64(result.value) <= abs_i64(arg.value)); in bw_floor2()
128 multiplicand = div64_s64(arg.value, abs_i64(significance.value)); in bw_ceil2()
129 result.value = abs_i64(significance.value) * multiplicand; in bw_ceil2()
[all …]
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| /linux/drivers/iio/accel/ |
| H A D | st_accel_core.c | 130 { .hz = 1, .value = 0x01, },
131 { .hz = 10, .value = 0x02, },
132 { .hz = 25, .value = 0x03, },
133 { .hz = 50, .value = 0x04, },
134 { .hz = 100, .value = 0x05, },
135 { .hz = 200, .value = 0x06, },
136 { .hz = 400, .value = 0x07, },
137 { .hz = 1600, .value = 0x08, },
155 .value = 0x00,
160 .value = 0x01,
[all …]
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| /linux/lib/crc/mips/ |
| H A D | crc32.h | 31 #define __CRC32(crc, value, op, SZ, TYPE) \ argument
40 : "r" (value)); \
43 #define _CRC32_crc32b(crc, value) __CRC32(crc, value, crc32b, 0, 0) argument
44 #define _CRC32_crc32h(crc, value) __CRC32(crc, value, crc32h, 1, 0) argument
45 #define _CRC32_crc32w(crc, value) __CRC32(crc, value, crc32w, 2, 0) argument
46 #define _CRC32_crc32d(crc, value) __CRC32(crc, value, crc32d, 3, 0) argument
47 #define _CRC32_crc32cb(crc, value) __CRC32(crc, value, crc32cb, 0, 1) argument
48 #define _CRC32_crc32ch(crc, value) __CRC32(crc, value, crc32ch, 1, 1) argument
49 #define _CRC32_crc32cw(crc, value) __CRC32(crc, value, crc32cw, 2, 1) argument
50 #define _CRC32_crc32cd(crc, value) __CRC32(crc, value, crc32cd, 3, 1) argument
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