Lines Matching refs:value
488 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl() local
490 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
492 return value; in tegra_sor_readl()
495 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() argument
498 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
499 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
546 u32 value; in tegra_clk_sor_pad_set_parent() local
548 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
549 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_clk_sor_pad_set_parent()
553 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; in tegra_clk_sor_pad_set_parent()
557 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; in tegra_clk_sor_pad_set_parent()
561 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
571 u32 value; in tegra_clk_sor_pad_get_parent() local
573 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_get_parent()
575 switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) { in tegra_clk_sor_pad_get_parent()
649 u32 value; in tegra_sor_power_up_lanes() local
655 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_up_lanes()
658 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | in tegra_sor_power_up_lanes()
661 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | in tegra_sor_power_up_lanes()
665 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); in tegra_sor_power_up_lanes()
667 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); in tegra_sor_power_up_lanes()
670 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()
672 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()
674 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_up_lanes()
677 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | in tegra_sor_power_up_lanes()
679 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_up_lanes()
684 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_up_lanes()
685 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_power_up_lanes()
691 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) in tegra_sor_power_up_lanes()
700 u32 value; in tegra_sor_power_down_lanes() local
703 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_down_lanes()
704 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | in tegra_sor_power_down_lanes()
706 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_down_lanes()
709 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | in tegra_sor_power_down_lanes()
711 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_down_lanes()
716 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_down_lanes()
717 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_power_down_lanes()
723 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) in tegra_sor_power_down_lanes()
731 u32 value; in tegra_sor_dp_precharge() local
734 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
737 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | in tegra_sor_dp_precharge()
740 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | in tegra_sor_dp_precharge()
744 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); in tegra_sor_dp_precharge()
746 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); in tegra_sor_dp_precharge()
749 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); in tegra_sor_dp_precharge()
751 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); in tegra_sor_dp_precharge()
753 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
757 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
758 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | in tegra_sor_dp_precharge()
760 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
765 u32 mask = 0x08, adj = 0, value; in tegra_sor_dp_term_calibrate() local
768 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
769 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_dp_term_calibrate()
770 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
772 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
773 value |= SOR_PLL1_TMDS_TERM; in tegra_sor_dp_term_calibrate()
774 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
779 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
780 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; in tegra_sor_dp_term_calibrate()
781 value |= SOR_PLL1_TMDS_TERMADJ(adj); in tegra_sor_dp_term_calibrate()
782 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
786 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
787 if (value & SOR_PLL1_TERM_COMPOUT) in tegra_sor_dp_term_calibrate()
793 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
794 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; in tegra_sor_dp_term_calibrate()
795 value |= SOR_PLL1_TMDS_TERMADJ(adj); in tegra_sor_dp_term_calibrate()
796 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
799 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
800 value |= SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_dp_term_calibrate()
801 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
809 u32 pattern = 0, tx_pu = 0, value; in tegra_sor_dp_link_apply_training() local
812 for (value = 0, i = 0; i < link->lanes; i++) { in tegra_sor_dp_link_apply_training()
827 value = SOR_DP_TPG_SCRAMBLER_GALIOS | in tegra_sor_dp_link_apply_training()
832 value = SOR_DP_TPG_SCRAMBLER_NONE | in tegra_sor_dp_link_apply_training()
837 value = SOR_DP_TPG_SCRAMBLER_NONE | in tegra_sor_dp_link_apply_training()
842 value = SOR_DP_TPG_SCRAMBLER_NONE | in tegra_sor_dp_link_apply_training()
851 value |= SOR_DP_TPG_CHANNEL_CODING; in tegra_sor_dp_link_apply_training()
853 pattern = pattern << 8 | value; in tegra_sor_dp_link_apply_training()
864 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_link_apply_training()
865 value &= ~SOR_DP_PADCTL_TX_PU_MASK; in tegra_sor_dp_link_apply_training()
866 value |= SOR_DP_PADCTL_TX_PU_ENABLE; in tegra_sor_dp_link_apply_training()
867 value |= SOR_DP_PADCTL_TX_PU(tx_pu); in tegra_sor_dp_link_apply_training()
868 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_link_apply_training()
879 u32 value; in tegra_sor_dp_link_configure() local
886 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_dp_link_configure()
887 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; in tegra_sor_dp_link_configure()
888 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); in tegra_sor_dp_link_configure()
889 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_dp_link_configure()
891 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_dp_link_configure()
892 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; in tegra_sor_dp_link_configure()
893 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); in tegra_sor_dp_link_configure()
896 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; in tegra_sor_dp_link_configure()
898 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_dp_link_configure()
903 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
904 value &= ~SOR_PLL1_LOADADJ_MASK; in tegra_sor_dp_link_configure()
908 value |= SOR_PLL1_LOADADJ(0x3); in tegra_sor_dp_link_configure()
912 value |= SOR_PLL1_LOADADJ(0x4); in tegra_sor_dp_link_configure()
916 value |= SOR_PLL1_LOADADJ(0x6); in tegra_sor_dp_link_configure()
920 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
923 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_dp_link_configure()
926 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_dp_link_configure()
928 value |= SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_dp_link_configure()
930 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_dp_link_configure()
972 u32 value; in tegra_sor_setup_pwm() local
974 value = tegra_sor_readl(sor, SOR_PWM_DIV); in tegra_sor_setup_pwm()
975 value &= ~SOR_PWM_DIV_MASK; in tegra_sor_setup_pwm()
976 value |= 0x400; /* period */ in tegra_sor_setup_pwm()
977 tegra_sor_writel(sor, value, SOR_PWM_DIV); in tegra_sor_setup_pwm()
979 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
980 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK; in tegra_sor_setup_pwm()
981 value |= 0x400; /* duty cycle */ in tegra_sor_setup_pwm()
982 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ in tegra_sor_setup_pwm()
983 value |= SOR_PWM_CTL_TRIGGER; in tegra_sor_setup_pwm()
984 tegra_sor_writel(sor, value, SOR_PWM_CTL); in tegra_sor_setup_pwm()
989 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
990 if ((value & SOR_PWM_CTL_TRIGGER) == 0) in tegra_sor_setup_pwm()
1001 unsigned long value, timeout; in tegra_sor_attach() local
1004 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
1005 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; in tegra_sor_attach()
1006 value |= SOR_SUPER_STATE_MODE_NORMAL; in tegra_sor_attach()
1007 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
1011 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
1012 value |= SOR_SUPER_STATE_ATTACHED; in tegra_sor_attach()
1013 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
1019 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_attach()
1020 if ((value & SOR_TEST_ATTACHED) != 0) in tegra_sor_attach()
1031 unsigned long value, timeout; in tegra_sor_wakeup() local
1037 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_wakeup()
1038 value &= SOR_TEST_HEAD_MODE_MASK; in tegra_sor_wakeup()
1040 if (value == SOR_TEST_HEAD_MODE_AWAKE) in tegra_sor_wakeup()
1051 u32 value; in tegra_sor_power_up() local
1053 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
1054 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; in tegra_sor_power_up()
1055 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_up()
1060 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
1061 if ((value & SOR_PWR_TRIGGER) == 0) in tegra_sor_power_up()
1248 u32 value; in tegra_sor_apply_config() local
1250 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
1251 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; in tegra_sor_apply_config()
1252 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size); in tegra_sor_apply_config()
1253 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
1255 value = tegra_sor_readl(sor, SOR_DP_CONFIG0); in tegra_sor_apply_config()
1256 value &= ~SOR_DP_CONFIG_WATERMARK_MASK; in tegra_sor_apply_config()
1257 value |= SOR_DP_CONFIG_WATERMARK(config->watermark); in tegra_sor_apply_config()
1259 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; in tegra_sor_apply_config()
1260 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count); in tegra_sor_apply_config()
1262 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; in tegra_sor_apply_config()
1263 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac); in tegra_sor_apply_config()
1266 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; in tegra_sor_apply_config()
1268 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; in tegra_sor_apply_config()
1270 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; in tegra_sor_apply_config()
1271 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; in tegra_sor_apply_config()
1272 tegra_sor_writel(sor, value, SOR_DP_CONFIG0); in tegra_sor_apply_config()
1274 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_apply_config()
1275 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; in tegra_sor_apply_config()
1276 value |= config->hblank_symbols & 0xffff; in tegra_sor_apply_config()
1277 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_apply_config()
1279 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_apply_config()
1280 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; in tegra_sor_apply_config()
1281 value |= config->vblank_symbols & 0xffff; in tegra_sor_apply_config()
1282 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_apply_config()
1291 u32 value; in tegra_sor_mode_set() local
1293 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_mode_set()
1294 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK; in tegra_sor_mode_set()
1295 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; in tegra_sor_mode_set()
1296 value &= ~SOR_STATE_ASY_OWNER_MASK; in tegra_sor_mode_set()
1298 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE | in tegra_sor_mode_set()
1302 value &= ~SOR_STATE_ASY_HSYNCPOL; in tegra_sor_mode_set()
1305 value |= SOR_STATE_ASY_HSYNCPOL; in tegra_sor_mode_set()
1308 value &= ~SOR_STATE_ASY_VSYNCPOL; in tegra_sor_mode_set()
1311 value |= SOR_STATE_ASY_VSYNCPOL; in tegra_sor_mode_set()
1315 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444; in tegra_sor_mode_set()
1319 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444; in tegra_sor_mode_set()
1323 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444; in tegra_sor_mode_set()
1327 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; in tegra_sor_mode_set()
1331 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444; in tegra_sor_mode_set()
1335 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; in tegra_sor_mode_set()
1339 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_mode_set()
1346 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); in tegra_sor_mode_set()
1347 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe); in tegra_sor_mode_set()
1353 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); in tegra_sor_mode_set()
1354 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe); in tegra_sor_mode_set()
1360 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); in tegra_sor_mode_set()
1361 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe); in tegra_sor_mode_set()
1367 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); in tegra_sor_mode_set()
1368 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe); in tegra_sor_mode_set()
1376 unsigned long value, timeout; in tegra_sor_detach() local
1379 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1380 value &= ~SOR_SUPER_STATE_MODE_NORMAL; in tegra_sor_detach()
1381 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1387 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_detach()
1388 if (value & SOR_PWR_MODE_SAFE) in tegra_sor_detach()
1392 if ((value & SOR_PWR_MODE_SAFE) == 0) in tegra_sor_detach()
1396 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1397 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; in tegra_sor_detach()
1398 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1402 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1403 value &= ~SOR_SUPER_STATE_ATTACHED; in tegra_sor_detach()
1404 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1410 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_detach()
1411 if ((value & SOR_TEST_ATTACHED) == 0) in tegra_sor_detach()
1417 if ((value & SOR_TEST_ATTACHED) != 0) in tegra_sor_detach()
1425 unsigned long value, timeout; in tegra_sor_power_down() local
1428 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
1429 value &= ~SOR_PWR_NORMAL_STATE_PU; in tegra_sor_power_down()
1430 value |= SOR_PWR_TRIGGER; in tegra_sor_power_down()
1431 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_down()
1436 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
1437 if ((value & SOR_PWR_TRIGGER) == 0) in tegra_sor_power_down()
1443 if ((value & SOR_PWR_TRIGGER) != 0) in tegra_sor_power_down()
1453 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1454 value |= SOR_PLL2_PORT_POWERDOWN; in tegra_sor_power_down()
1455 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1459 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_power_down()
1460 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; in tegra_sor_power_down()
1461 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_power_down()
1463 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1464 value |= SOR_PLL2_SEQ_PLLCAPPD; in tegra_sor_power_down()
1465 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_power_down()
1466 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1475 u32 value; in tegra_sor_crc_wait() local
1480 value = tegra_sor_readl(sor, SOR_CRCA); in tegra_sor_crc_wait()
1481 if (value & SOR_CRCA_VALID) in tegra_sor_crc_wait()
1497 u32 value; in tegra_sor_show_crc() local
1506 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_show_crc()
1507 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; in tegra_sor_show_crc()
1508 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_show_crc()
1510 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); in tegra_sor_show_crc()
1511 value |= SOR_CRC_CNTRL_ENABLE; in tegra_sor_show_crc()
1512 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); in tegra_sor_show_crc()
1514 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_show_crc()
1515 value &= ~SOR_TEST_CRC_POST_SERIALIZE; in tegra_sor_show_crc()
1516 tegra_sor_writel(sor, value, SOR_TEST); in tegra_sor_show_crc()
1523 value = tegra_sor_readl(sor, SOR_CRCB); in tegra_sor_show_crc()
1525 seq_printf(s, "%08x\n", value); in tegra_sor_show_crc()
1853 u32 value = 0; in tegra_sor_hdmi_subpack() local
1857 value = (value << 8) | ptr[i - 1]; in tegra_sor_hdmi_subpack()
1859 return value; in tegra_sor_hdmi_subpack()
1868 u32 value; in tegra_sor_hdmi_write_infopack() local
1889 value = INFOFRAME_HEADER_TYPE(ptr[0]) | in tegra_sor_hdmi_write_infopack()
1892 tegra_sor_writel(sor, value, offset); in tegra_sor_hdmi_write_infopack()
1903 value = tegra_sor_hdmi_subpack(&ptr[i], num); in tegra_sor_hdmi_write_infopack()
1904 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
1908 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num); in tegra_sor_hdmi_write_infopack()
1909 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
1919 u32 value; in tegra_sor_hdmi_setup_avi_infoframe() local
1923 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1924 value &= ~INFOFRAME_CTRL_SINGLE; in tegra_sor_hdmi_setup_avi_infoframe()
1925 value &= ~INFOFRAME_CTRL_OTHER; in tegra_sor_hdmi_setup_avi_infoframe()
1926 value &= ~INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_setup_avi_infoframe()
1927 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1945 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1946 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; in tegra_sor_hdmi_setup_avi_infoframe()
1947 value |= INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_setup_avi_infoframe()
1948 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1973 u32 value; in tegra_sor_audio_prepare() local
1980 value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0; in tegra_sor_audio_prepare()
1981 tegra_sor_writel(sor, value, SOR_INT_ENABLE); in tegra_sor_audio_prepare()
1982 tegra_sor_writel(sor, value, SOR_INT_MASK); in tegra_sor_audio_prepare()
1986 value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD; in tegra_sor_audio_prepare()
1987 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE); in tegra_sor_audio_prepare()
1999 u32 value; in tegra_sor_audio_enable() local
2001 value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL); in tegra_sor_audio_enable()
2004 value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK); in tegra_sor_audio_enable()
2005 value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA); in tegra_sor_audio_enable()
2009 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL; in tegra_sor_audio_enable()
2011 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL; in tegra_sor_audio_enable()
2013 value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH; in tegra_sor_audio_enable()
2015 tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL); in tegra_sor_audio_enable()
2025 u32 value; in tegra_sor_hdmi_enable_audio_infoframe() local
2044 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_enable_audio_infoframe()
2045 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; in tegra_sor_hdmi_enable_audio_infoframe()
2046 value |= INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_enable_audio_infoframe()
2047 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_enable_audio_infoframe()
2054 u32 value; in tegra_sor_hdmi_audio_enable() local
2060 value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH | in tegra_sor_hdmi_audio_enable()
2063 tegra_sor_writel(sor, value, SOR_HDMI_SPARE); in tegra_sor_hdmi_audio_enable()
2066 value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0); in tegra_sor_hdmi_audio_enable()
2067 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW); in tegra_sor_hdmi_audio_enable()
2070 value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE; in tegra_sor_hdmi_audio_enable()
2071 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH); in tegra_sor_hdmi_audio_enable()
2074 value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP; in tegra_sor_hdmi_audio_enable()
2075 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2077 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2078 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320); in tegra_sor_hdmi_audio_enable()
2090 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2091 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480); in tegra_sor_hdmi_audio_enable()
2094 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2095 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960); in tegra_sor_hdmi_audio_enable()
2098 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2099 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920); in tegra_sor_hdmi_audio_enable()
2102 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2103 value &= ~SOR_HDMI_AUDIO_N_RESET; in tegra_sor_hdmi_audio_enable()
2104 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2111 u32 value; in tegra_sor_hdmi_disable_audio_infoframe() local
2113 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
2114 value &= ~INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_disable_audio_infoframe()
2115 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
2137 u32 value; in tegra_sor_hdmi_disable_scrambling() local
2139 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); in tegra_sor_hdmi_disable_scrambling()
2140 value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; in tegra_sor_hdmi_disable_scrambling()
2141 value &= ~SOR_HDMI2_CTRL_SCRAMBLE; in tegra_sor_hdmi_disable_scrambling()
2142 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_disable_scrambling()
2163 u32 value; in tegra_sor_hdmi_enable_scrambling() local
2165 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); in tegra_sor_hdmi_enable_scrambling()
2166 value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; in tegra_sor_hdmi_enable_scrambling()
2167 value |= SOR_HDMI2_CTRL_SCRAMBLE; in tegra_sor_hdmi_enable_scrambling()
2168 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_enable_scrambling()
2210 u32 value; in tegra_sor_hdmi_disable() local
2224 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_disable()
2227 value &= ~SOR1_TIMING_CYA; in tegra_sor_hdmi_disable()
2229 value &= ~SOR_ENABLE(sor->index); in tegra_sor_hdmi_disable()
2231 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_disable()
2257 u32 value; in tegra_sor_hdmi_enable() local
2285 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2286 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; in tegra_sor_hdmi_enable()
2287 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2291 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2292 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3; in tegra_sor_hdmi_enable()
2293 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2295 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2296 value &= ~SOR_PLL0_VCOPD; in tegra_sor_hdmi_enable()
2297 value &= ~SOR_PLL0_PWR; in tegra_sor_hdmi_enable()
2298 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2300 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2301 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_hdmi_enable()
2302 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2306 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2307 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; in tegra_sor_hdmi_enable()
2308 value &= ~SOR_PLL2_PORT_POWERDOWN; in tegra_sor_hdmi_enable()
2309 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2313 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2314 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | in tegra_sor_hdmi_enable()
2316 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2319 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2320 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0) in tegra_sor_hdmi_enable()
2326 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | in tegra_sor_hdmi_enable()
2328 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2331 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2332 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_hdmi_enable()
2338 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2339 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; in tegra_sor_hdmi_enable()
2340 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_sor_hdmi_enable()
2344 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70; in tegra_sor_hdmi_enable()
2347 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40; in tegra_sor_hdmi_enable()
2350 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; in tegra_sor_hdmi_enable()
2351 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2356 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2357 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; in tegra_sor_hdmi_enable()
2358 value |= SOR_DP_LINKCTL_LANE_COUNT(4); in tegra_sor_hdmi_enable()
2359 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2361 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2362 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; in tegra_sor_hdmi_enable()
2363 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_hdmi_enable()
2364 value &= ~SOR_DP_SPARE_SEQ_ENABLE; in tegra_sor_hdmi_enable()
2365 value &= ~SOR_DP_SPARE_MACRO_SOR_CLK; in tegra_sor_hdmi_enable()
2366 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2368 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) | in tegra_sor_hdmi_enable()
2370 tegra_sor_writel(sor, value, SOR_SEQ_CTL); in tegra_sor_hdmi_enable()
2372 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT | in tegra_sor_hdmi_enable()
2374 tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); in tegra_sor_hdmi_enable()
2375 tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); in tegra_sor_hdmi_enable()
2379 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div); in tegra_sor_hdmi_enable()
2380 tegra_sor_writel(sor, value, SOR_REFCLK); in tegra_sor_hdmi_enable()
2384 for (value = 0, i = 0; i < 5; i++) in tegra_sor_hdmi_enable()
2385 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | in tegra_sor_hdmi_enable()
2389 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_hdmi_enable()
2433 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); in tegra_sor_hdmi_enable()
2437 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED; in tegra_sor_hdmi_enable()
2439 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); in tegra_sor_hdmi_enable()
2444 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) | in tegra_sor_hdmi_enable()
2446 tegra_sor_writel(sor, value, SOR_HDMI_CTRL); in tegra_sor_hdmi_enable()
2454 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE | in tegra_sor_hdmi_enable()
2456 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); in tegra_sor_hdmi_enable()
2458 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start); in tegra_sor_hdmi_enable()
2459 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); in tegra_sor_hdmi_enable()
2461 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_sor_hdmi_enable()
2462 value |= H_PULSE2_ENABLE; in tegra_sor_hdmi_enable()
2463 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_sor_hdmi_enable()
2475 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2476 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; in tegra_sor_hdmi_enable()
2477 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A; in tegra_sor_hdmi_enable()
2478 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2481 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2482 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_hdmi_enable()
2483 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2493 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2494 value &= ~SOR_PLL0_ICHPMP_MASK; in tegra_sor_hdmi_enable()
2495 value &= ~SOR_PLL0_FILTER_MASK; in tegra_sor_hdmi_enable()
2496 value &= ~SOR_PLL0_VCOCAP_MASK; in tegra_sor_hdmi_enable()
2497 value |= SOR_PLL0_ICHPMP(settings->ichpmp); in tegra_sor_hdmi_enable()
2498 value |= SOR_PLL0_FILTER(settings->filter); in tegra_sor_hdmi_enable()
2499 value |= SOR_PLL0_VCOCAP(settings->vcocap); in tegra_sor_hdmi_enable()
2500 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2503 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2504 value &= ~SOR_PLL1_LOADADJ_MASK; in tegra_sor_hdmi_enable()
2505 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; in tegra_sor_hdmi_enable()
2506 value |= SOR_PLL1_LOADADJ(settings->loadadj); in tegra_sor_hdmi_enable()
2507 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj); in tegra_sor_hdmi_enable()
2508 value |= SOR_PLL1_TMDS_TERM; in tegra_sor_hdmi_enable()
2509 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2511 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2512 value &= ~SOR_PLL3_BG_TEMP_COEF_MASK; in tegra_sor_hdmi_enable()
2513 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK; in tegra_sor_hdmi_enable()
2514 value &= ~SOR_PLL3_AVDD10_LEVEL_MASK; in tegra_sor_hdmi_enable()
2515 value &= ~SOR_PLL3_AVDD14_LEVEL_MASK; in tegra_sor_hdmi_enable()
2516 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef); in tegra_sor_hdmi_enable()
2517 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level); in tegra_sor_hdmi_enable()
2518 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level); in tegra_sor_hdmi_enable()
2519 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level); in tegra_sor_hdmi_enable()
2520 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2522 value = settings->drive_current[3] << 24 | in tegra_sor_hdmi_enable()
2526 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_hdmi_enable()
2528 value = settings->preemphasis[3] << 24 | in tegra_sor_hdmi_enable()
2532 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); in tegra_sor_hdmi_enable()
2534 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2535 value &= ~SOR_DP_PADCTL_TX_PU_MASK; in tegra_sor_hdmi_enable()
2536 value |= SOR_DP_PADCTL_TX_PU_ENABLE; in tegra_sor_hdmi_enable()
2537 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value); in tegra_sor_hdmi_enable()
2538 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2540 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2541 value &= ~SOR_DP_PADCTL_SPAREPLL_MASK; in tegra_sor_hdmi_enable()
2542 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll); in tegra_sor_hdmi_enable()
2543 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2546 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2547 value |= SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_hdmi_enable()
2548 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2552 value = VSYNC_H_POSITION(1); in tegra_sor_hdmi_enable()
2553 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); in tegra_sor_hdmi_enable()
2556 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL); in tegra_sor_hdmi_enable()
2557 value &= ~DITHER_CONTROL_MASK; in tegra_sor_hdmi_enable()
2558 value &= ~BASE_COLOR_SIZE_MASK; in tegra_sor_hdmi_enable()
2562 value |= BASE_COLOR_SIZE_666; in tegra_sor_hdmi_enable()
2566 value |= BASE_COLOR_SIZE_888; in tegra_sor_hdmi_enable()
2570 value |= BASE_COLOR_SIZE_101010; in tegra_sor_hdmi_enable()
2574 value |= BASE_COLOR_SIZE_121212; in tegra_sor_hdmi_enable()
2579 value |= BASE_COLOR_SIZE_888; in tegra_sor_hdmi_enable()
2583 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); in tegra_sor_hdmi_enable()
2586 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2587 value &= ~SOR_STATE_ASY_OWNER_MASK; in tegra_sor_hdmi_enable()
2588 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe); in tegra_sor_hdmi_enable()
2589 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2596 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2597 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK; in tegra_sor_hdmi_enable()
2598 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK; in tegra_sor_hdmi_enable()
2599 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2602 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2603 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK; in tegra_sor_hdmi_enable()
2604 value |= SOR_HEAD_STATE_COLORSPACE_RGB; in tegra_sor_hdmi_enable()
2605 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2612 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2613 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; in tegra_sor_hdmi_enable()
2614 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2621 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_enable()
2624 value |= SOR1_TIMING_CYA; in tegra_sor_hdmi_enable()
2626 value |= SOR_ENABLE(sor->index); in tegra_sor_hdmi_enable()
2628 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_enable()
2631 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2632 value &= ~PROTOCOL_MASK; in tegra_sor_hdmi_enable()
2633 value |= PROTOCOL_SINGLE_TMDS_A; in tegra_sor_hdmi_enable()
2634 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2658 u32 value; in tegra_sor_dp_disable() local
2682 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_disable()
2683 value &= ~SOR_ENABLE(sor->index); in tegra_sor_dp_disable()
2684 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_disable()
2687 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_dp_disable()
2688 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; in tegra_sor_dp_disable()
2689 value &= ~SOR_STATE_ASY_SUBOWNER_MASK; in tegra_sor_dp_disable()
2690 value &= ~SOR_STATE_ASY_OWNER_MASK; in tegra_sor_dp_disable()
2691 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_dp_disable()
2727 u32 value; in tegra_sor_dp_enable() local
2768 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2769 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; in tegra_sor_dp_enable()
2770 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2774 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2775 value |= SOR_PLL3_PLL_VDD_MODE_3V3; in tegra_sor_dp_enable()
2776 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2778 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2779 value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR); in tegra_sor_dp_enable()
2780 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2782 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2783 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_dp_enable()
2784 value |= SOR_PLL2_SEQ_PLLCAPPD; in tegra_sor_dp_enable()
2785 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2789 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2790 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; in tegra_sor_dp_enable()
2791 value &= ~SOR_PLL2_PORT_POWERDOWN; in tegra_sor_dp_enable()
2792 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2794 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_dp_enable()
2795 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_sor_dp_enable()
2798 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; in tegra_sor_dp_enable()
2800 value |= SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK; in tegra_sor_dp_enable()
2802 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_dp_enable()
2806 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_dp_enable()
2809 value |= SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_dp_enable()
2811 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_dp_enable()
2813 value |= SOR_DP_SPARE_SEQ_ENABLE; in tegra_sor_dp_enable()
2814 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_dp_enable()
2819 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2820 value &= ~SOR_PLL0_ICHPMP_MASK; in tegra_sor_dp_enable()
2821 value &= ~SOR_PLL0_VCOCAP_MASK; in tegra_sor_dp_enable()
2822 value |= SOR_PLL0_ICHPMP(0x1); in tegra_sor_dp_enable()
2823 value |= SOR_PLL0_VCOCAP(0x3); in tegra_sor_dp_enable()
2824 value |= SOR_PLL0_RESISTOR_EXT; in tegra_sor_dp_enable()
2825 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2828 for (value = 0, i = 0; i < 5; i++) in tegra_sor_dp_enable()
2829 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | in tegra_sor_dp_enable()
2833 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_dp_enable()
2867 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_dp_enable()
2868 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; in tegra_sor_dp_enable()
2869 value |= SOR_STATE_ASY_PROTOCOL_DP_A; in tegra_sor_dp_enable()
2870 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_dp_enable()
2873 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_dp_enable()
2874 value |= SOR_DP_LINKCTL_ENABLE; in tegra_sor_dp_enable()
2875 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_dp_enable()
2902 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | in tegra_sor_dp_enable()
2904 tegra_sor_writel(sor, value, SOR_CSTM); in tegra_sor_dp_enable()
2923 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_enable()
2924 value |= SOR_ENABLE(sor->index); in tegra_sor_dp_enable()
2925 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_enable()
3645 u32 value; in tegra_sor_parse_dt() local
3649 err = of_property_read_u32(np, "nvidia,interface", &value); in tegra_sor_parse_dt()
3653 sor->index = value; in tegra_sor_parse_dt()
3684 u32 value; in tegra_sor_irq() local
3686 value = tegra_sor_readl(sor, SOR_INT_STATUS); in tegra_sor_irq()
3687 tegra_sor_writel(sor, value, SOR_INT_STATUS); in tegra_sor_irq()
3689 if (value & SOR_INT_CODEC_SCRATCH0) { in tegra_sor_irq()
3690 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0); in tegra_sor_irq()
3692 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) { in tegra_sor_irq()
3695 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK; in tegra_sor_irq()