| /linux/drivers/gpu/drm/tegra/ |
| H A D | mipi-phy.c | 16 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, in mipi_dphy_timing_get_default() argument
19 timing->clkmiss = 0; in mipi_dphy_timing_get_default()
20 timing->clkpost = 70 + 52 * period; in mipi_dphy_timing_get_default()
21 timing->clkpre = 8; in mipi_dphy_timing_get_default()
22 timing->clkprepare = 65; in mipi_dphy_timing_get_default()
23 timing->clksettle = 95; in mipi_dphy_timing_get_default()
24 timing->clktermen = 0; in mipi_dphy_timing_get_default()
25 timing->clktrail = 80; in mipi_dphy_timing_get_default()
26 timing->clkzero = 260; in mipi_dphy_timing_get_default()
27 timing->dtermen = 0; in mipi_dphy_timing_get_default()
[all …]
|
| /linux/drivers/clk/tegra/ |
| H A D | clk-tegra124-emc.c | 120 struct emc_timing *timing = NULL; in emc_determine_rate() local
136 timing = tegra->timings + i; in emc_determine_rate()
138 if (timing->rate < req->rate && i != t - 1) in emc_determine_rate()
141 if (timing->rate > req->max_rate) { in emc_determine_rate()
147 if (timing->rate < req->min_rate) in emc_determine_rate()
150 req->rate = timing->rate; in emc_determine_rate()
154 if (timing) { in emc_determine_rate()
155 req->rate = timing->rate; in emc_determine_rate()
210 struct emc_timing *timing) in emc_set_timing() argument
221 pr_debug("going to rate %ld prate %ld p %s\n", timing->rate, in emc_set_timing()
[all …]
|
| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| H A D | timing.c | 33 u32 timing = 0; in nvbios_timingTe() local
37 timing = nvbios_rd32(bios, bit_P.offset + 4); in nvbios_timingTe()
40 timing = nvbios_rd32(bios, bit_P.offset + 8); in nvbios_timingTe()
42 if (timing) { in nvbios_timingTe()
43 *ver = nvbios_rd08(bios, timing + 0); in nvbios_timingTe()
46 *hdr = nvbios_rd08(bios, timing + 1); in nvbios_timingTe()
47 *cnt = nvbios_rd08(bios, timing + 2); in nvbios_timingTe()
48 *len = nvbios_rd08(bios, timing + 3); in nvbios_timingTe()
51 return timing; in nvbios_timingTe()
53 *hdr = nvbios_rd08(bios, timing + 1); in nvbios_timingTe()
[all …]
|
| /linux/drivers/video/fbdev/ |
| H A D | gbefb.c | 38 struct gbe_timing_info timing; member
411 static void gbefb_setup_flatpanel(struct gbe_timing_info *timing) in gbefb_setup_flatpanel() argument
417 (timing->flags & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1); in gbefb_setup_flatpanel()
419 (timing->flags & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1); in gbefb_setup_flatpanel()
427 timing->pll_m = 4; in gbefb_setup_flatpanel()
428 timing->pll_n = 1; in gbefb_setup_flatpanel()
429 timing->pll_p = 0; in gbefb_setup_flatpanel()
456 struct gbe_timing_info *timing) in compute_gbe_timing() argument
504 if (timing) { in compute_gbe_timing()
505 timing->width = var->xres; in compute_gbe_timing()
[all …]
|
| /linux/drivers/video/fbdev/via/ |
| H A D | via_modesetting.c | 18 void via_set_primary_timing(const struct via_display_timing *timing) in via_set_primary_timing() argument
22 raw.hor_total = timing->hor_total / 8 - 5; in via_set_primary_timing()
23 raw.hor_addr = timing->hor_addr / 8 - 1; in via_set_primary_timing()
24 raw.hor_blank_start = timing->hor_blank_start / 8 - 1; in via_set_primary_timing()
25 raw.hor_blank_end = timing->hor_blank_end / 8 - 1; in via_set_primary_timing()
26 raw.hor_sync_start = timing->hor_sync_start / 8; in via_set_primary_timing()
27 raw.hor_sync_end = timing->hor_sync_end / 8; in via_set_primary_timing()
28 raw.ver_total = timing->ver_total - 2; in via_set_primary_timing()
29 raw.ver_addr = timing->ver_addr - 1; in via_set_primary_timing()
30 raw.ver_blank_start = timing->ver_blank_start - 1; in via_set_primary_timing()
[all …]
|
| /linux/drivers/gpu/drm/sti/ |
| H A D | sti_awg_utils.c | 122 struct awg_timing *timing) in awg_generate_line_signal() argument
127 if (timing->trailing_pixels > 0) { in awg_generate_line_signal()
129 val = timing->blanking_level; in awg_generate_line_signal()
132 val = timing->trailing_pixels - 1 + AWG_DELAY; in awg_generate_line_signal()
137 val = timing->blanking_level; in awg_generate_line_signal()
138 ret |= awg_generate_instr((timing->trailing_pixels > 0) ? SET : RPLSET, in awg_generate_line_signal()
141 if (timing->blanking_pixels > 0) { in awg_generate_line_signal()
143 val = timing->active_pixels - 1; in awg_generate_line_signal()
147 val = timing->blanking_level; in awg_generate_line_signal()
156 struct awg_timing *timing) in sti_awg_generate_code_data_enable_mode() argument
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn201/ |
| H A D | dcn201_optc.c | 70 const struct dc_crtc_timing *timing) in optc201_validate_timing() argument
77 ASSERT(timing != NULL); in optc201_validate_timing()
79 v_blank = (timing->v_total - timing->v_addressable - in optc201_validate_timing()
80 timing->v_border_top - timing->v_border_bottom); in optc201_validate_timing()
82 h_blank = (timing->h_total - timing->h_addressable - in optc201_validate_timing()
83 timing->h_border_right - in optc201_validate_timing()
84 timing->h_border_left); in optc201_validate_timing()
86 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE && in optc201_validate_timing()
87 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING && in optc201_validate_timing()
88 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM && in optc201_validate_timing()
[all …]
|
| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| H A D | ramnv50.c | 73 nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing) in nv50_ram_timing_calc() argument
98 timing[6] = (0x2d + T(CL) - T(CWL) + in nv50_ram_timing_calc()
104 timing[6] = (0x2b + T(CL) - T(CWL)) << 16 | in nv50_ram_timing_calc()
109 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); in nv50_ram_timing_calc()
110 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in nv50_ram_timing_calc()
114 timing[2] = (T(CWL) - 1) << 24 | in nv50_ram_timing_calc()
118 timing[3] = (unkt3b - 2 + T(CL)) << 24 | in nv50_ram_timing_calc()
122 timing[4] = (cur4 & 0xffff0000) | in nv50_ram_timing_calc()
125 timing[5] = T(RFC) << 24 | in nv50_ram_timing_calc()
129 timing[7] = (cur7 & 0xff00ffff) | (T(CL) - 1) << 16; in nv50_ram_timing_calc()
[all …]
|
| H A D | ramgt215.c | 348 gt215_ram_timing_calc(struct gt215_ram *ram, u32 *timing) in gt215_ram_timing_calc() argument
374 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); in gt215_ram_timing_calc()
375 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in gt215_ram_timing_calc()
379 timing[2] = (T(CWL) - 1) << 24 | in gt215_ram_timing_calc()
383 timing[3] = (cur3 & 0x00ff0000) | in gt215_ram_timing_calc()
387 timing[4] = T(20) << 24 | in gt215_ram_timing_calc()
391 timing[5] = T(RFC) << 24 | in gt215_ram_timing_calc()
395 timing[6] = (0x5a + T(CL)) << 16 | in gt215_ram_timing_calc()
398 timing[7] = (cur7 & 0xff000000) | in gt215_ram_timing_calc()
401 timing[8] = cur8 & 0xffffff00; in gt215_ram_timing_calc()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dsc/ |
| H A D | dc_dsc.c | 62 const struct dc_crtc_timing *timing, const uint32_t kbps) in apply_128b_132b_stream_overhead() argument
69 if (!timing->flags.DSC) { in apply_128b_132b_stream_overhead()
74 bpp = dc_fixpt_div_int(bpp, timing->pix_clk_100hz / 10); in apply_128b_132b_stream_overhead()
79 overhead_factor = dc_fixpt_from_int(timing->h_addressable); in apply_128b_132b_stream_overhead()
94 const struct dc_crtc_timing *timing, in dc_bandwidth_in_kbps_from_timing() argument
100 if (timing->flags.DSC) in dc_bandwidth_in_kbps_from_timing()
101 return dc_dsc_stream_bandwidth_in_kbps(timing, in dc_bandwidth_in_kbps_from_timing()
102 timing->dsc_cfg.bits_per_pixel, in dc_bandwidth_in_kbps_from_timing()
103 timing->dsc_cfg.num_slices_h, in dc_bandwidth_in_kbps_from_timing()
104 timing in dc_bandwidth_in_kbps_from_timing()
464 dc_dsc_compute_bandwidth_range(const struct display_stream_compressor * dsc,uint32_t dsc_min_slice_height_override,uint32_t min_bpp_x16,uint32_t max_bpp_x16,const struct dsc_dec_dpcd_caps * dsc_sink_caps,const struct dc_crtc_timing * timing,const enum dc_link_encoding_format link_encoding,struct dc_dsc_bw_range * range) dc_dsc_compute_bandwidth_range() argument
498 dc_dsc_dump_encoder_caps(const struct display_stream_compressor * dsc,const struct dc_crtc_timing * timing) dc_dsc_dump_encoder_caps() argument
638 get_min_dsc_slice_count_for_odm(const struct display_stream_compressor * dsc,const struct dsc_enc_caps * dsc_enc_caps,const struct dc_crtc_timing * timing) get_min_dsc_slice_count_for_odm() argument
767 compute_bpp_x16_from_target_bandwidth(const uint32_t bandwidth_in_kbps,const struct dc_crtc_timing * timing,const uint32_t num_slices_h,const uint32_t bpp_increment_div,const bool is_dp) compute_bpp_x16_from_target_bandwidth() argument
799 decide_dsc_bandwidth_range(const uint32_t min_bpp_x16,const uint32_t max_bpp_x16,const uint32_t num_slices_h,const struct dsc_enc_caps * dsc_caps,const struct dc_crtc_timing * timing,const enum dc_link_encoding_format link_encoding,struct dc_dsc_bw_range * range) decide_dsc_bandwidth_range() argument
855 decide_dsc_target_bpp_x16(const struct dc_dsc_policy * policy,const struct dc_dsc_config_options * options,const struct dsc_enc_caps * dsc_common_caps,const int target_bandwidth_kbps,const struct dc_crtc_timing * timing,const int num_slices_h,const enum dc_link_encoding_format link_encoding,int * target_bpp_x16) decide_dsc_target_bpp_x16() argument
1046 setup_dsc_config(const struct dsc_dec_dpcd_caps * dsc_sink_caps,const struct dsc_enc_caps * dsc_enc_caps,int target_bandwidth_kbps,const struct dc_crtc_timing * timing,const struct dc_dsc_config_options * options,const enum dc_link_encoding_format link_encoding,int min_slices_h,struct dc_dsc_config * dsc_cfg) setup_dsc_config() argument
1296 dc_dsc_compute_config(const struct display_stream_compressor * dsc,const struct dsc_dec_dpcd_caps * dsc_sink_caps,const struct dc_dsc_config_options * options,uint32_t target_bandwidth_kbps,const struct dc_crtc_timing * timing,const enum dc_link_encoding_format link_encoding,struct dc_dsc_config * dsc_cfg) dc_dsc_compute_config() argument
1318 dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing * timing,uint32_t bpp_x16,uint32_t num_slices_h,bool is_dp) dc_dsc_stream_bandwidth_in_kbps() argument
1335 dc_dsc_stream_bandwidth_overhead_in_kbps(const struct dc_crtc_timing * timing,const int num_slices_h,const bool is_dp) dc_dsc_stream_bandwidth_overhead_in_kbps() argument
1360 dc_dsc_get_policy_for_timing(const struct dc_crtc_timing * timing,uint32_t max_target_bpp_limit_override_x16,struct dc_dsc_policy * policy,const enum dc_link_encoding_format link_encoding) dc_dsc_get_policy_for_timing() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/ |
| H A D | dml21_translation_helper.c | 85 max_hw_v_total -= stream->timing.v_front_porch + 1; in calc_max_hardware_v_total()
91 static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cfg *timing, in populate_dml21_timing_config_from_stream_state()
96 const unsigned int min_v_front_porch = (stream->timing.flags.INTERLACE != 0) ? 2 : 1; in populate_dml21_timing_config_from_stream_state()
102 timing->h_active = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right + pipe_ctx->dsc_padding_params.dsc_hactive_padding; in populate_dml21_timing_config_from_stream_state()
103 timing->v_active = stream->timing.v_addressable + stream->timing in populate_dml21_timing_config_from_stream_state()
88 populate_dml21_timing_config_from_stream_state(struct dml2_timing_cfg * timing,struct dc_stream_state * stream,struct pipe_ctx * pipe_ctx,struct dml2_context * dml_ctx) populate_dml21_timing_config_from_stream_state() argument
[all...] |
| /linux/drivers/media/i2c/ |
| H A D | bt819.c | 60 struct timing { struct
70 static struct timing timing_data[] = { argument
175 struct timing *timing = &timing_data[(decoder->norm & V4L2_STD_525_60) ? 1 : 0]; in bt819_init() local
178 (((timing->vdelay >> 8) & 0x03) << 6) | in bt819_init()
179 (((timing->vactive >> 8) & 0x03) << 4) | in bt819_init()
180 (((timing->hdelay >> 8) & 0x03) << 2) | in bt819_init()
181 ((timing->hactive >> 8) & 0x03); in bt819_init()
182 init[0x04 * 2 - 1] = timing->vdelay & 0xff; in bt819_init()
183 init[0x05 * 2 - 1] = timing in bt819_init()
238 struct timing *timing = NULL; bt819_s_std() local
[all...] |
| /linux/drivers/gpu/drm/msm/dsi/phy/ |
| H A D | dsi_phy_20nm.c | 11 struct msm_dsi_dphy_timing *timing) in dsi_20nm_dphy_set_timing() argument
15 writel(DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero), in dsi_20nm_dphy_set_timing()
17 writel(DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail), in dsi_20nm_dphy_set_timing()
19 writel(DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare), in dsi_20nm_dphy_set_timing()
21 if (timing->clk_zero & BIT(8)) in dsi_20nm_dphy_set_timing()
24 writel(DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit), in dsi_20nm_dphy_set_timing()
26 writel(DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero), in dsi_20nm_dphy_set_timing()
28 writel(DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare), in dsi_20nm_dphy_set_timing()
30 writel(DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail), in dsi_20nm_dphy_set_timing()
32 writel(DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst), in dsi_20nm_dphy_set_timing()
[all …]
|
| /linux/drivers/ata/ |
| H A D | pata_triflex.c | 76 u32 timing = 0; in triflex_load_timing() local
88 timing = 0x0103;break; in triflex_load_timing()
90 timing = 0x0203;break; in triflex_load_timing()
92 timing = 0x0808;break; in triflex_load_timing()
96 timing = 0x0F0F;break; in triflex_load_timing()
98 timing = 0x0202;break; in triflex_load_timing()
100 timing = 0x0204;break; in triflex_load_timing()
102 timing = 0x0404;break; in triflex_load_timing()
104 timing = 0x0508;break; in triflex_load_timing()
106 timing = 0x0808;break; in triflex_load_timing()
[all …]
|
| H A D | pata_sis.c | 314 t1 &= 0xC0C00FFF; /* Mask out timing */ in sis_133_set_piomode()
341 u16 timing; in sis_old_set_dmamode() local
346 pci_read_config_word(pdev, drive_pci, &timing); in sis_old_set_dmamode()
349 /* bits 3-0 hold recovery timing bits 8-10 active timing and in sis_old_set_dmamode()
351 timing &= ~0x870F; in sis_old_set_dmamode()
352 timing |= mwdma_bits[speed]; in sis_old_set_dmamode()
356 timing &= ~0x6000; in sis_old_set_dmamode()
357 timing |= udma_bits[speed]; in sis_old_set_dmamode()
359 pci_write_config_word(pdev, drive_pci, timing); in sis_old_set_dmamode()
380 u16 timing; sis_66_set_dmamode() local
419 u8 timing; sis_100_set_dmamode() local
453 u8 timing; sis_133_early_set_dmamode() local
[all...] |
| H A D | pata_cs5530.c | 76 u32 tuning, timing = 0; in cs5530_set_dmamode() local
84 timing = 0x00921250;break; in cs5530_set_dmamode()
86 timing = 0x00911140;break; in cs5530_set_dmamode()
88 timing = 0x00911030;break; in cs5530_set_dmamode()
90 timing = 0x00077771;break; in cs5530_set_dmamode()
92 timing = 0x00012121;break; in cs5530_set_dmamode()
94 timing = 0x00002020;break; in cs5530_set_dmamode()
99 timing |= (tuning & 0x80000000UL); in cs5530_set_dmamode()
101 iowrite32(timing, base + 0x04); in cs5530_set_dmamode()
103 if (timing & 0x00100000) in cs5530_set_dmamode()
[all …]
|
| H A D | pata_cmd640.c | 54 struct cmd640_reg *timing = ap->private_data; in cmd640_set_piomode() local
68 /* The second channel has shared timings and the setup timing is in cmd640_set_piomode()
100 /* Load setup timing */ in cmd640_set_piomode()
116 timing->reg58[adev->devno] = (t.active << 4) | t.recover; in cmd640_set_piomode()
134 struct cmd640_reg *timing = ap->private_data; in cmd640_qc_issue() local
136 if (ap->port_no != 0 && adev->devno != timing->last) { in cmd640_qc_issue()
137 pci_write_config_byte(pdev, DRWTIM23, timing->reg58[adev->devno]); in cmd640_qc_issue()
138 timing->last = adev->devno; in cmd640_qc_issue()
154 struct cmd640_reg *timing; in cmd640_port_start() local
156 timing in cmd640_port_start()
[all...] |
| /linux/drivers/gpu/drm/amd/display/modules/freesync/ |
| H A D | freesync.c | 120 * 10000) * stream->timing.h_total, in calc_duration_in_us_from_v_total()
121 stream->timing.pix_clk_100hz)); in calc_duration_in_us_from_v_total()
131 max_hw_v_total -= stream->timing.v_front_porch + 1; in calc_max_hardware_v_total()
145 return stream->timing.v_total; in mod_freesync_calc_v_total_from_refresh()
151 if (refresh_in_uhz <= stream->timing.min_refresh_in_uhz) { in mod_freesync_calc_v_total_from_refresh()
157 frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)), in mod_freesync_calc_v_total_from_refresh()
158 stream->timing.h_total), 1000000); in mod_freesync_calc_v_total_from_refresh()
159 } else if (refresh_in_uhz >= stream->timing.max_refresh_in_uhz) { in mod_freesync_calc_v_total_from_refresh()
165 frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)), in mod_freesync_calc_v_total_from_refresh()
166 stream->timing.h_total) + (1000000 - 1), 1000000); in mod_freesync_calc_v_total_from_refresh()
[all …]
|
| /linux/drivers/gpu/drm/mediatek/ |
| H A D | mtk_dsi.c | 250 struct mtk_phy_timing *timing = &dsi->phy_timing; in mtk_dsi_phy_timconfig() local
252 timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1; in mtk_dsi_phy_timconfig()
253 timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000; in mtk_dsi_phy_timconfig()
254 timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 - in mtk_dsi_phy_timconfig()
255 timing->da_hs_prepare; in mtk_dsi_phy_timconfig()
256 timing->da_hs_trail = timing->da_hs_prepare + 1; in mtk_dsi_phy_timconfig()
258 timing->ta_go = 4 * timing->lpx - 2; in mtk_dsi_phy_timconfig()
259 timing in mtk_dsi_phy_timconfig()
512 struct mtk_phy_timing *timing = &dsi->phy_timing; mtk_dsi_config_vdo_timing_per_line_lp() local
[all...] |
| /linux/drivers/memory/samsung/ |
| H A D | exynos-srom.c | 71 u32 timing[6]; in exynos_srom_configure_bank() local
80 if (of_property_read_u32_array(np, "samsung,srom-timing", timing, in exynos_srom_configure_bank()
81 ARRAY_SIZE(timing))) in exynos_srom_configure_bank()
94 writel_relaxed(pmc | (timing[0] << EXYNOS_SROM_BCX__TACP__SHIFT) | in exynos_srom_configure_bank()
95 (timing[1] << EXYNOS_SROM_BCX__TCAH__SHIFT) | in exynos_srom_configure_bank()
96 (timing[2] << EXYNOS_SROM_BCX__TCOH__SHIFT) | in exynos_srom_configure_bank()
97 (timing[3] << EXYNOS_SROM_BCX__TACC__SHIFT) | in exynos_srom_configure_bank()
98 (timing[4] << EXYNOS_SROM_BCX__TCOS__SHIFT) | in exynos_srom_configure_bank()
99 (timing[5] << EXYNOS_SROM_BCX__TACS__SHIFT), in exynos_srom_configure_bank()
|
| /linux/drivers/pcmcia/ |
| H A D | sa11xx_base.c | 81 struct soc_pcmcia_timing timing; in sa1100_pcmcia_set_mecr() local
86 soc_common_pcmcia_get_timing(skt, &timing); in sa1100_pcmcia_set_mecr()
88 bs_io = skt->ops->get_timing(skt, cpu_clock, timing.io); in sa1100_pcmcia_set_mecr()
89 bs_mem = skt->ops->get_timing(skt, cpu_clock, timing.mem); in sa1100_pcmcia_set_mecr()
90 bs_attr = skt->ops->get_timing(skt, cpu_clock, timing.attr); in sa1100_pcmcia_set_mecr()
146 struct soc_pcmcia_timing timing; in sa1100_pcmcia_show_timing() local
151 soc_common_pcmcia_get_timing(skt, &timing); in sa1100_pcmcia_show_timing()
153 p+=sprintf(p, "I/O : %uns (%uns)\n", timing.io, in sa1100_pcmcia_show_timing()
156 p+=sprintf(p, "attribute: %uns (%uns)\n", timing.attr, in sa1100_pcmcia_show_timing()
159 p+=sprintf(p, "common : %uns (%uns)\n", timing.mem, in sa1100_pcmcia_show_timing()
|
| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_dsc.h | 85 const struct dc_crtc_timing *timing,
94 const struct dc_crtc_timing *timing,
98 uint32_t dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing *timing,
102 const struct dc_crtc_timing *timing,
109 const struct dc_crtc_timing *timing);
116 void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,
|
| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_utils.c | 340 …(double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.bpc; in dml2_core_utils_get_stream_output_bpp()
341 …if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.ena… in dml2_core_utils_get_stream_output_bpp()
357 …} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.… in dml2_core_utils_get_stream_output_bpp()
358 …_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.dsc_compressed… in dml2_core_utils_get_stream_output_bpp()
364 …display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable); in dml2_core_utils_get_stream_output_bpp()
580 phantom->timing.v_total = meta->v_total; in create_phantom_stream_from_main_stream()
581 phantom->timing.v_active = meta->v_active; in create_phantom_stream_from_main_stream()
582 phantom->timing.v_front_porch = meta->v_front_porch; in create_phantom_stream_from_main_stream()
583 …phantom->timing.v_blank_end = phantom->timing.v_total - phantom->timing.v_front_porch - phantom->t… in create_phantom_stream_from_main_stream()
584 phantom->timing.vblank_nom = phantom->timing.v_total - phantom->timing.v_active; in create_phantom_stream_from_main_stream()
[all …]
|
| /linux/Documentation/driver-api/memory-devices/ |
| H A D | ti-gpmc.rst | 20 GPMC generic timing calculation:
29 generic timing routine was developed to achieve above requirements.
37 happen that timing as specified by peripheral datasheet is not present
38 in timing structure, in this scenario, try to correlate peripheral
39 timing to the one available. If that doesn't work, try to add a new
40 field as required by peripheral, educate generic timing routine to
45 Generic timing routine has been verified to work properly on
48 A word of caution: generic timing routine has been developed based
50 custom timing routines, a kind of reverse engineering without
52 in mainline having custom timing routine) and by simulation.
[all …]
|
| /linux/drivers/nvmem/ |
| H A D | vf610-ocotp.c | 94 int timing; member
118 u32 timing; in vf610_ocotp_calculate_timing() local
127 timing = BF(relax, OCOTP_TIMING_RELAX); in vf610_ocotp_calculate_timing()
128 timing |= BF(strobe_read, OCOTP_TIMING_STROBE_READ); in vf610_ocotp_calculate_timing()
129 timing |= BF(strobe_prog, OCOTP_TIMING_STROBE_PROG); in vf610_ocotp_calculate_timing()
131 return timing; in vf610_ocotp_calculate_timing()
158 writel(ocotp->timing, base + OCOTP_TIMING); in vf610_ocotp_read()
233 ocotp_dev->timing = vf610_ocotp_calculate_timing(ocotp_dev); in vf610_ocotp_probe()
|