Searched refs:root_clock_optimization (Results 1 – 8 of 8) sorted by relevance
124 dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1); in dccg42_set_physymclk()140 dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1); in dccg42_set_physymclk()156 dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1); in dccg42_set_physymclk()172 dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1); in dccg42_set_physymclk()188 dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1); in dccg42_set_physymclk()207 dccg->ctx->dc->debug.root_clock_optimization.bits.hdmistream ? 0 : 1); in dccg42_disable_hdmistreamclk()220 …HDMICHARCLK0_ROOT_GATE_DISABLE, dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar ? 0 : 1… in dccg42_disable_hdmicharclk()291 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) { in dccg42_init()296 if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) { in dccg42_init()302 if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar) in dccg42_init()[all …]
971 .root_clock_optimization = {2092 dc->debug.root_clock_optimization.u32All = 0; in dcn314_resource_construct()
789 .root_clock_optimization = {
802 .root_clock_optimization = {
782 .root_clock_optimization = {
1203 union root_clock_optimization_options root_clock_optimization; member
766 .root_clock_optimization = {
819 .root_clock_optimization = {