| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| H A D | dcn303_resource.c | 675 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_dwbc_create()
710 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_mmhubbub_create()
954 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn303_resource_destruct()
984 for (i = 0; i < pool->res_cap->num_ddc; i++) { in dcn303_resource_destruct()
997 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn303_resource_destruct()
1002 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn303_resource_destruct()
1009 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn303_resource_destruct()
1033 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn303_resource_destruct()
1154 pool->res_cap = &res_cap_dcn303; in dcn303_resource_construct()
1162 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn303_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| H A D | dcn302_resource.c | 714 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_dwbc_create()
749 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_mmhubbub_create()
1010 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn302_resource_destruct()
1040 for (i = 0; i < pool->res_cap->num_ddc; i++) { in dcn302_resource_destruct()
1053 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn302_resource_destruct()
1058 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn302_resource_destruct()
1065 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn302_resource_destruct()
1089 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn302_resource_destruct()
1213 pool->res_cap = &res_cap_dcn302; in dcn302_resource_construct()
1221 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn302_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| H A D | dcn301_resource.c | 1056 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn301_destruct()
1086 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn301_destruct()
1099 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn301_destruct()
1104 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn301_destruct()
1111 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn301_destruct()
1134 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn301_destruct()
1150 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn301_destruct()
1179 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_dwbc_create()
1203 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_mmhubbub_create()
1301 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; in init_soc_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| H A D | dcn316_resource.c | 1112 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1382 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn316_resource_destruct()
1412 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn316_resource_destruct()
1425 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn316_resource_destruct()
1430 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn316_resource_destruct()
1437 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn316_resource_destruct()
1460 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn316_resource_destruct()
1476 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn316_resource_destruct()
1510 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1534 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 1178 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1445 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn314_resource_destruct()
1474 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn314_resource_destruct()
1487 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn314_resource_destruct()
1492 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn314_resource_destruct()
1499 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn314_resource_destruct()
1522 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn314_resource_destruct()
1538 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn314_resource_destruct()
1575 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1599 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| H A D | dcn315_resource.c | 1119 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1387 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn315_resource_destruct()
1417 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn315_resource_destruct()
1430 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn315_resource_destruct()
1435 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn315_resource_destruct()
1442 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn315_resource_destruct()
1465 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn315_resource_destruct()
1481 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn315_resource_destruct()
1518 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1542 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.c | 1120 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1386 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn31_resource_destruct()
1416 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn31_resource_destruct()
1429 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn31_resource_destruct()
1434 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn31_resource_destruct()
1441 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn31_resource_destruct()
1464 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn31_resource_destruct()
1480 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn31_resource_destruct()
1517 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1541 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| H A D | dcn36_resource.c | 1113 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1443 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn36_resource_destruct()
1473 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn36_resource_destruct()
1486 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn36_resource_destruct()
1491 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn36_resource_destruct()
1498 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn36_resource_destruct()
1521 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn36_resource_destruct()
1537 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn36_resource_destruct()
1590 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create()
1628 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.c | 1126 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1456 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn35_resource_destruct()
1486 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn35_resource_destruct()
1499 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn35_resource_destruct()
1504 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn35_resource_destruct()
1511 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn35_resource_destruct()
1534 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn35_resource_destruct()
1550 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn35_resource_destruct()
1603 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create()
1641 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| H A D | dcn351_resource.c | 1106 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1436 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn351_resource_destruct()
1466 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn351_resource_destruct()
1479 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn351_resource_destruct()
1484 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn351_resource_destruct()
1491 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn351_resource_destruct()
1514 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn351_resource_destruct()
1530 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn351_resource_destruct()
1583 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create()
1621 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 1085 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn30_resource_destruct()
1115 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn30_resource_destruct()
1128 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn30_resource_destruct()
1133 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn30_resource_destruct()
1140 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn30_resource_destruct()
1163 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn30_resource_destruct()
1219 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create()
1243 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create()
1442 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn30_acquire_post_bldn_3dlut()
1472 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn30_release_post_bldn_3dlut()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce80/ |
| H A D | dce80_resource.c | 379 static const struct resource_caps res_cap = { variable
857 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_resource_destruct()
932 pool->base.res_cap = &res_cap; in dce80_construct()
940 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
941 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce80_construct()
1061 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_construct()
1135 pool->base.res_cap = &res_cap_81; in dce81_construct()
1261 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce81_construct()
1335 pool->base.res_cap = &res_cap_83; in dce83_construct()
1459 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce83_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce60/ |
| H A D | dce60_resource.c | 379 static const struct resource_caps res_cap = { variable
851 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_resource_destruct()
926 pool->base.res_cap = &res_cap; in dce60_construct()
934 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
935 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce60_construct()
1050 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_construct()
1124 pool->base.res_cap = &res_cap_61; in dce61_construct()
1248 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce61_construct()
1322 pool->base.res_cap = &res_cap_64; in dce64_construct()
1445 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce64_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| H A D | dcn321_resource.c | 1373 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn321_resource_destruct()
1402 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn321_resource_destruct()
1415 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn321_resource_destruct()
1420 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn321_resource_destruct()
1427 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn321_resource_destruct()
1450 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn321_resource_destruct()
1466 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn321_resource_destruct()
1488 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn321_dwbc_create()
1516 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn321_mmhubbub_create()
1671 pool->base.res_cap = &res_cap_dcn321; in dcn321_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| H A D | dcn401_resource.c | 1428 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn401_resource_destruct()
1458 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn401_resource_destruct()
1471 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn401_resource_destruct()
1476 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn401_resource_destruct()
1483 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn401_resource_destruct()
1506 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn401_resource_destruct()
1522 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn401_resource_destruct()
1549 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn401_dwbc_create()
1579 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn401_mmhubbub_create()
1890 pool->base.res_cap = &res_cap_dcn4_01; in dcn401_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 1392 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn32_resource_destruct()
1422 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn32_resource_destruct()
1435 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn32_resource_destruct()
1440 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn32_resource_destruct()
1447 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn32_resource_destruct()
1470 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn32_resource_destruct()
1486 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn32_resource_destruct()
1508 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn32_dwbc_create()
1536 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn32_mmhubbub_create()
1626 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn32_release_post_bldn_3dlut()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 1094 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn20_resource_destruct()
1124 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn20_resource_destruct()
1137 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn20_resource_destruct()
1142 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn20_resource_destruct()
1149 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn20_resource_destruct()
1339 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) { in dcn20_acquire_dsc()
1353 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_acquire_dsc()
1367 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_release_dsc()
2241 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_dwbc_create()
2263 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce100/ |
| H A D | dce100_resource.c | 379 static const struct resource_caps res_cap = { variable
808 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce100_resource_destruct()
1042 pool->base.res_cap = &res_cap; in dce100_resource_construct()
1117 pool->base.pipe_count = res_cap.num_timing_generator; in dce100_resource_construct()
1118 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce100_resource_construct()
1175 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce100_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce120/ |
| H A D | dce120_resource.c | 499 static const struct resource_caps res_cap = { variable
629 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce120_resource_destruct()
1077 pool->base.res_cap = &res_cap; in dce120_resource_construct()
1081 pool->base.pipe_count = res_cap.num_timing_generator; in dce120_resource_construct()
1082 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce120_resource_construct()
1228 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce120_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| H A D | dcn201_resource.c | 950 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn201_resource_destruct()
955 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn201_resource_destruct()
1097 pool->base.res_cap = &res_cap_dnc201; in dcn201_resource_construct()
1196 dcn201_ip.max_num_otg = pool->base.res_cap->num_timing_generator; in dcn201_resource_construct()
1231 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn201_resource_construct()
1240 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn201_resource_construct()
1256 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn201_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| H A D | dcn21_resource.c | 667 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn21_resource_destruct()
696 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn21_resource_destruct()
709 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn21_resource_destruct()
714 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn21_resource_destruct()
721 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn21_resource_destruct()
1397 pool->base.res_cap = &res_cap_rn; in dcn21_resource_construct()
1407 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn21_resource_construct()
1621 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn21_resource_construct()
1657 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn21_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| H A D | dcn10_resource.c | 489 static const struct resource_caps res_cap = { variable
945 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn10_resource_destruct()
1329 pool->base.res_cap = &rv2_res_cap; in dcn10_resource_construct()
1331 pool->base.res_cap = &res_cap; in dcn10_resource_construct()
1345 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn10_resource_construct()
1613 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn10_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce112/ |
| H A D | dce112_resource.c | 805 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce112_resource_destruct()
1236 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id); in dce112_resource_construct()
1243 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1244 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1379 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce112_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| H A D | dcn201_hwseq.c | 189 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); in dcn201_init_blank()
300 for (i = 0; i < res_pool->res_cap->num_opp; i++) { in dcn201_init_hw()
333 for (i = 0; i < res_pool->res_cap->num_dwb; i++) in dcn201_init_hw()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce110/ |
| H A D | dce110_resource.c | 840 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce110_resource_destruct()
1362 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); in dce110_resource_construct()
1369 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1371 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1488 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce110_resource_construct()
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