| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| H A D | dcn303_resource.c | 703 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_dwbc_create()
738 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_mmhubbub_create()
983 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn303_resource_destruct()
1018 for (i = 0; i < pool->res_cap->num_ddc; i++) { in dcn303_resource_destruct()
1031 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn303_resource_destruct()
1036 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn303_resource_destruct()
1043 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn303_resource_destruct()
1067 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn303_resource_destruct()
1189 pool->res_cap = &res_cap_dcn303; in dcn303_resource_construct()
1197 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn303_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| H A D | dcn302_resource.c | 742 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_dwbc_create()
777 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_mmhubbub_create()
1039 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn302_resource_destruct()
1074 for (i = 0; i < pool->res_cap->num_ddc; i++) { in dcn302_resource_destruct()
1087 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn302_resource_destruct()
1092 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn302_resource_destruct()
1099 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn302_resource_destruct()
1123 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn302_resource_destruct()
1248 pool->res_cap = &res_cap_dcn302; in dcn302_resource_construct()
1256 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn302_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| H A D | dcn301_resource.c | 1085 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn301_destruct()
1121 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn301_destruct()
1134 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn301_destruct()
1139 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn301_destruct()
1146 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn301_destruct()
1169 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn301_destruct()
1185 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn301_destruct()
1214 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_dwbc_create()
1238 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_mmhubbub_create()
1336 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; in init_soc_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 1207 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1474 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn314_resource_destruct()
1507 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn314_resource_destruct()
1520 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn314_resource_destruct()
1525 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn314_resource_destruct()
1532 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn314_resource_destruct()
1555 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn314_resource_destruct()
1571 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn314_resource_destruct()
1608 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1632 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| H A D | dcn316_resource.c | 1141 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1411 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn316_resource_destruct()
1445 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn316_resource_destruct()
1458 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn316_resource_destruct()
1463 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn316_resource_destruct()
1470 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn316_resource_destruct()
1493 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn316_resource_destruct()
1509 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn316_resource_destruct()
1543 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1567 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.c | 1156 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1486 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn35_resource_destruct()
1516 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn35_resource_destruct()
1529 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn35_resource_destruct()
1534 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn35_resource_destruct()
1541 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn35_resource_destruct()
1564 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn35_resource_destruct()
1580 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn35_resource_destruct()
1638 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create()
1676 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.c | 1149 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1415 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn31_resource_destruct()
1449 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn31_resource_destruct()
1462 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn31_resource_destruct()
1467 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn31_resource_destruct()
1474 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn31_resource_destruct()
1497 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn31_resource_destruct()
1513 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn31_resource_destruct()
1550 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1574 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| H A D | dcn315_resource.c | 1148 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1416 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn315_resource_destruct()
1450 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn315_resource_destruct()
1463 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn315_resource_destruct()
1468 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn315_resource_destruct()
1475 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn315_resource_destruct()
1498 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn315_resource_destruct()
1514 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn315_resource_destruct()
1551 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1575 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| H A D | dcn36_resource.c | 1143 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1473 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn36_resource_destruct()
1503 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn36_resource_destruct()
1516 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn36_resource_destruct()
1521 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn36_resource_destruct()
1528 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn36_resource_destruct()
1551 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn36_resource_destruct()
1567 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn36_resource_destruct()
1625 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create()
1663 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| H A D | dcn351_resource.c | 1136 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1466 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn351_resource_destruct()
1496 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn351_resource_destruct()
1509 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn351_resource_destruct()
1514 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn351_resource_destruct()
1521 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn351_resource_destruct()
1544 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn351_resource_destruct()
1560 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn351_resource_destruct()
1618 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create()
1656 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 1114 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn30_resource_destruct()
1150 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn30_resource_destruct()
1163 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn30_resource_destruct()
1168 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn30_resource_destruct()
1175 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn30_resource_destruct()
1198 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn30_resource_destruct()
1254 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create()
1278 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create()
1477 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn30_acquire_post_bldn_3dlut()
1507 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn30_release_post_bldn_3dlut()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce80/ |
| H A D | dce80_resource.c | 379 static const struct resource_caps res_cap = { variable
857 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_resource_destruct()
932 pool->base.res_cap = &res_cap; in dce80_construct()
940 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
941 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce80_construct()
1061 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_construct()
1135 pool->base.res_cap = &res_cap_81; in dce81_construct()
1261 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce81_construct()
1335 pool->base.res_cap = &res_cap_83; in dce83_construct()
1459 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce83_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce60/ |
| H A D | dce60_resource.c | 379 static const struct resource_caps res_cap = { variable
850 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_resource_destruct()
925 pool->base.res_cap = &res_cap; in dce60_construct()
933 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
934 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce60_construct()
1049 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_construct()
1123 pool->base.res_cap = &res_cap_61; in dce61_construct()
1247 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce61_construct()
1321 pool->base.res_cap = &res_cap_64; in dce64_construct()
1444 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce64_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| H A D | dcn321_resource.c | 1403 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn321_resource_destruct()
1432 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn321_resource_destruct()
1445 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn321_resource_destruct()
1450 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn321_resource_destruct()
1457 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn321_resource_destruct()
1480 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn321_resource_destruct()
1496 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn321_resource_destruct()
1523 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn321_dwbc_create()
1551 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn321_mmhubbub_create()
1707 pool->base.res_cap = &res_cap_dcn321; in dcn321_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 1123 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn20_resource_destruct()
1159 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn20_resource_destruct()
1172 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn20_resource_destruct()
1177 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn20_resource_destruct()
1184 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn20_resource_destruct()
1375 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) { in dcn20_acquire_dsc()
1389 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_acquire_dsc()
1403 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_release_dsc()
2293 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_dwbc_create()
2315 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_mmhubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce100/ |
| H A D | dce100_resource.c | 379 static const struct resource_caps res_cap = { variable
807 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce100_resource_destruct()
1045 pool->base.res_cap = &res_cap; in dce100_resource_construct()
1120 pool->base.pipe_count = res_cap.num_timing_generator; in dce100_resource_construct()
1121 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce100_resource_construct()
1178 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce100_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 1422 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn32_resource_destruct()
1452 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn32_resource_destruct()
1465 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn32_resource_destruct()
1470 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn32_resource_destruct()
1477 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn32_resource_destruct()
1500 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn32_resource_destruct()
1516 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn32_resource_destruct()
1543 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn32_dwbc_create()
1571 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn32_mmhubbub_create()
1661 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn32_release_post_bldn_3dlut()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce120/ |
| H A D | dce120_resource.c | 499 static const struct resource_caps res_cap = { variable
629 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce120_resource_destruct()
1079 pool->base.res_cap = &res_cap; in dce120_resource_construct()
1083 pool->base.pipe_count = res_cap.num_timing_generator; in dce120_resource_construct()
1084 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce120_resource_construct()
1230 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce120_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| H A D | dcn201_resource.c | 983 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn201_resource_destruct()
988 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn201_resource_destruct()
1131 pool->base.res_cap = &res_cap_dnc201; in dcn201_resource_construct()
1230 dcn201_ip.max_num_otg = pool->base.res_cap->num_timing_generator; in dcn201_resource_construct()
1265 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn201_resource_construct()
1274 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn201_resource_construct()
1290 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn201_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| H A D | dcn21_resource.c | 687 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn21_resource_destruct()
722 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn21_resource_destruct()
735 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn21_resource_destruct()
740 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn21_resource_destruct()
747 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn21_resource_destruct()
1438 pool->base.res_cap = &res_cap_rn; in dcn21_resource_construct()
1448 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn21_resource_construct()
1662 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn21_resource_construct()
1706 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn21_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| H A D | dcn10_resource.c | 517 static const struct resource_caps res_cap = { variable
979 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn10_resource_destruct()
1372 pool->base.res_cap = &rv2_res_cap; in dcn10_resource_construct()
1374 pool->base.res_cap = &res_cap; in dcn10_resource_construct()
1388 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn10_resource_construct()
1656 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn10_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce112/ |
| H A D | dce112_resource.c | 807 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce112_resource_destruct()
1242 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id); in dce112_resource_construct()
1249 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1250 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1385 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce112_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| H A D | dcn201_hwseq.c | 189 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); in dcn201_init_blank()
300 for (i = 0; i < res_pool->res_cap->num_opp; i++) { in dcn201_init_hw()
333 for (i = 0; i < res_pool->res_cap->num_dwb; i++) in dcn201_init_hw()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce110/ |
| H A D | dce110_resource.c | 842 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce110_resource_destruct()
1369 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); in dce110_resource_construct()
1376 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1378 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1495 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce110_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 603 dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn31_update_bw_bounding_box_fpu()
675 dcn3_15_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn315_update_bw_bounding_box_fpu()
742 dcn3_16_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn316_update_bw_bounding_box_fpu()
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