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Searched refs:res_cap (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/resource/dce60/
H A Ddce60_resource.c379 static const struct resource_caps res_cap = { variable
850 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_resource_destruct()
925 pool->base.res_cap = &res_cap; in dce60_construct()
933 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
934 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce60_construct()
1049 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_construct()
1123 pool->base.res_cap = &res_cap_61; in dce61_construct()
1247 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce61_construct()
1321 pool->base.res_cap = &res_cap_64; in dce64_construct()
1444 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce64_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c983 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn201_resource_destruct()
988 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn201_resource_destruct()
1131 pool->base.res_cap = &res_cap_dnc201; in dcn201_resource_construct()
1230 dcn201_ip.max_num_otg = pool->base.res_cap->num_timing_generator; in dcn201_resource_construct()
1265 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn201_resource_construct()
1274 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn201_resource_construct()
1290 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn201_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c189 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); in dcn201_init_blank()
300 for (i = 0; i < res_pool->res_cap->num_opp; i++) { in dcn201_init_hw()
333 for (i = 0; i < res_pool->res_cap->num_dwb; i++) in dcn201_init_hw()