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Searched refs:pg_cntl (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/pg/dcn42/
H A Ddcn42_pg_cntl.c10 #define TO_DCN_PG_CNTL(pg_cntl)\ argument
11 container_of(pg_cntl, struct dcn_pg_cntl, base)
23 pg_cntl->ctx->logger
36 static void pg_cntl42_save_and_disable_global_fgcg_rep(struct pg_cntl *pg_cntl, in pg_cntl42_save_and_disable_global_fgcg_rep() argument
39 struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); in pg_cntl42_save_and_disable_global_fgcg_rep()
42 if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_get_global_fgcg_status) in pg_cntl42_save_and_disable_global_fgcg_rep()
43 …state->dccg_global_ono_rep_fgcg = pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_get_global_fgcg_st… in pg_cntl42_save_and_disable_global_fgcg_rep()
47 if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg) in pg_cntl42_save_and_disable_global_fgcg_rep()
48 …pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg,… in pg_cntl42_save_and_disable_global_fgcg_rep()
53 static void pg_cntl42_restore_global_fgcg_rep(struct pg_cntl *pg_cntl, in pg_cntl42_restore_global_fgcg_rep() argument
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/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dpg_cntl.h32 struct pg_cntl { struct
40 void (*dsc_pg_control)(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bool power_on); argument
41 void (*hubp_dpp_pg_control)(struct pg_cntl *pg_cntl, unsigned int hubp_dpp_inst, bool power_on);
42 void (*hpo_pg_control)(struct pg_cntl *pg_cntl, bool power_on);
43 void (*io_clk_pg_control)(struct pg_cntl *pg_cntl, bool power_on);
44 void (*plane_otg_pg_control)(struct pg_cntl *pg_cntl, bool power_on);
45 void (*mpcc_pg_control)(struct pg_cntl *pg_cntl, unsigned int mpcc_inst, bool power_on);
46 void (*opp_pg_control)(struct pg_cntl *pg_cntl, unsigned int opp_inst, bool power_on);
47 void (*optc_pg_control)(struct pg_cntl *pg_cntl, unsigned int optc_inst, bool power_on);
48 void (*dwb_pg_control)(struct pg_cntl *pg_cntl, bool power_on);
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/linux/drivers/gpu/drm/amd/display/dc/pg/dcn35/
H A Ddcn35_pg_cntl.h166 struct pg_cntl base;
172 void pg_cntl35_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bool power_on);
173 void pg_cntl35_hubp_dpp_pg_control(struct pg_cntl *pg_cntl,
175 void pg_cntl35_hpo_pg_control(struct pg_cntl *pg_cntl, bool power_on);
176 void pg_cntl35_io_clk_pg_control(struct pg_cntl *pg_cntl, bool power_on);
177 void pg_cntl35_plane_otg_pg_control(struct pg_cntl *pg_cntl, bool power_on);
178 void pg_cntl35_mpcc_pg_control(struct pg_cntl *pg_cntl,
180 void pg_cntl35_opp_pg_control(struct pg_cntl *pg_cntl,
182 void pg_cntl35_optc_pg_control(struct pg_cntl *pg_cntl,
184 void pg_cntl35_dwb_pg_control(struct pg_cntl *pg_cntl, bool power_on);
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/
H A Ddcn36_resource.c1699 if (pool->base.pg_cntl != NULL) in dcn36_resource_destruct()
1700 dcn_pg_cntl_destroy(&pool->base.pg_cntl); in dcn36_resource_destruct()
2157 pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask); in dcn36_resource_construct()
2158 if (pool->base.pg_cntl == NULL) { in dcn36_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c1712 if (pool->base.pg_cntl != NULL) in dcn35_resource_destruct()
1713 dcn_pg_cntl_destroy(&pool->base.pg_cntl); in dcn35_resource_destruct()
2187 pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask); in dcn35_resource_construct()
2188 if (pool->base.pg_cntl == NULL) { in dcn35_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c1692 if (pool->base.pg_cntl != NULL) in dcn351_resource_destruct()
1693 dcn_pg_cntl_destroy(&pool->base.pg_cntl); in dcn351_resource_destruct()
2159 pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask); in dcn351_resource_construct()
2160 if (pool->base.pg_cntl == NULL) { in dcn351_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn42b/
H A Ddcn42b_resource.c1634 if (pool->base.pg_cntl != NULL) in dcn42b_resource_destruct()
1635 dcn_pg_cntl_destroy(&pool->base.pg_cntl); in dcn42b_resource_destruct()
2208 pool->base.pg_cntl = pg_cntl42_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask); in dcn42b_resource_construct()
2209 if (pool->base.pg_cntl == NULL) { in dcn42b_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn42/
H A Ddcn42_resource.c1643 if (pool->base.pg_cntl != NULL) in dcn42_resource_destruct()
1644 dcn_pg_cntl_destroy(&pool->base.pg_cntl); in dcn42_resource_destruct()
2234 pool->base.pg_cntl = pg_cntl42_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask); in dcn42_resource_construct()
2235 if (pool->base.pg_cntl == NULL) { in dcn42_resource_construct()