| /linux/arch/powerpc/kernel/ |
| H A D | rtas-proc.c | 508 int num_states = 0; in ppc_rtas_process_sensor() local
517 num_states = sizeof(key_switch) / sizeof(char *); in ppc_rtas_process_sensor()
518 if (state < num_states) { in ppc_rtas_process_sensor()
525 num_states = sizeof(enclosure_switch) / sizeof(char *); in ppc_rtas_process_sensor()
526 if (state < num_states) { in ppc_rtas_process_sensor()
538 num_states = sizeof(lid_status) / sizeof(char *); in ppc_rtas_process_sensor()
539 if (state < num_states) { in ppc_rtas_process_sensor()
546 num_states = sizeof(power_source) / sizeof(char *); in ppc_rtas_process_sensor()
547 if (state < num_states) { in ppc_rtas_process_sensor()
558 num_states = sizeof(battery_remaining) / sizeof(char *); in ppc_rtas_process_sensor()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 1704 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1708 …alidate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING || vlevel == context->bw_ctx.dml.soc.num_states || in dcn30_internal_validate_bw()
1722 if (vlevel < context->bw_ctx.dml.soc.num_states) { in dcn30_internal_validate_bw()
1732 if (vlevel == context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1899 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; in dcn30_internal_validate_bw()
2121 …_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn30_validate_bandwidth()
2137 unsigned int num_states = 0; in dcn30_update_bw_bounding_box() local
2230 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()
2232 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box()
2233 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn30_update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_wrapper_fpu.c | 61 dml2_translate_soc_states(in_dc, out, in_dc->dml.soc.num_states); in initialize_dml2_soc_states()
107 s->mode_support_params.in_start_state_idx = dml2->v20.dml_core_ctx.states.num_states - 1; in pack_and_call_dml_mode_support_ex()
194 for (i = 0; i < dml2->v20.dml_core_ctx.states.num_states; i++) { in calculate_lowest_supported_state_for_temp_read()
199 for (j = 0; j < dml2->v20.dml_core_ctx.states.num_states; j++) { in calculate_lowest_supported_state_for_temp_read()
224 for (i = 0; i < dml2->v20.dml_core_ctx.states.num_states; i++) { in calculate_lowest_supported_state_for_temp_read()
469 (lowest_state_idx < dml2->v20.dml_core_ctx.states.num_states - 1)) { in dml2_validate_and_build_resource()
470 lowest_state_idx = dml2->v20.dml_core_ctx.states.num_states - 1; in dml2_validate_and_build_resource()
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| H A D | dml2_translation_helper.c | 361 p->in_states->num_states = 2; in dml2_init_soc_states()
397 p->in_states->num_states = 2; in dml2_init_soc_states()
434 p->in_states->num_states = 2; in dml2_init_soc_states()
471 for (i = 0; i < p->in_states->num_states; i++) { in dml2_init_soc_states()
526 if (dml2->config.bbox_overrides.clks_table.num_states) { in dml2_init_soc_states()
527 p->in_states->num_states = dml2->config.bbox_overrides.clks_table.num_states; in dml2_init_soc_states()
571 for (i = 0; i < p->in_states->num_states; i++) { in dml2_init_soc_states()
590 for (i = 0; i < p->in_states->num_states; i++) { in dml2_init_soc_states()
610 p->out_states->num_states = p->in_states->num_states; in dml2_init_soc_states()
719 void dml2_translate_soc_states(const struct dc *dc, struct soc_states_st *out, int num_states) in dml2_translate_soc_states() argument
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| /linux/net/netfilter/ipvs/ |
| H A D | ip_vs_proto_ah_esp.c | 118 .num_states = 1,
140 .num_states = 1,
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| H A D | ip_vs_proto_udp.c | 478 .num_states = IP_VS_UDP_S_LAST,
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| H A D | ip_vs_proto_sctp.c | 573 .num_states = IP_VS_SCTP_S_LAST,
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| H A D | ip_vs_proto_tcp.c | 720 .num_states = IP_VS_TCP_S_LAST,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 143 .num_states = 1,
300 if (vlevel < context->bw_ctx.dml.vba.soc.num_states && in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
1413 if (new_vlevel < context->bw_ctx.dml.soc.num_states) { in try_odm_power_optimization_and_revalidate()
1469 if (*vlevel < context->bw_ctx.dml.soc.num_states) { in dcn32_full_validate_bw_helper()
1489 …(*vlevel == context->bw_ctx.dml.soc.num_states || (vba->DRAMSpeedPerState[*vlevel] != vba->DRAMSpe… in dcn32_full_validate_bw_helper()
1505 if (*vlevel == context->bw_ctx.dml.soc.num_states && in dcn32_full_validate_bw_helper()
1530 for (i = *vlevel; i < context->bw_ctx.dml.soc.num_states; i++) { in dcn32_full_validate_bw_helper()
1537 if (*vlevel < context->bw_ctx.dml.soc.num_states in dcn32_full_validate_bw_helper()
1569 if (*vlevel < context->bw_ctx.dml.soc.num_states) { in dcn32_full_validate_bw_helper()
2113 int vlevel = context->bw_ctx.dml.soc.num_states; in dcn32_internal_validate_bw()
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| H A D | display_mode_vba_32.c | 112 mode_lib->vba.MaxDppclk[v->soc.num_states - 1])); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1654 start_state = v->soc.num_states - 1; in mode_support_configuration()
1658 for (i = v->soc.num_states - 1; i >= start_state; i--) { in mode_support_configuration()
1705 || i == v->soc.num_states - 1) in mode_support_configuration()
1710 || i == v->soc.num_states - 1 in mode_support_configuration()
1712 && (!mode_lib->vba.FCLKChangeRequirementFinal || i == v->soc.num_states - 1 in mode_support_configuration()
1741 start_state = v->soc.num_states - 1; in dml32_ModeSupportAndSystemConfigurationFull()
2033 for (i = start_state; i < v->soc.num_states; i++) { in dml32_ModeSupportAndSystemConfigurationFull()
2048 mode_lib->vba.MaxDispclk[v->soc.num_states - 1], in dml32_ModeSupportAndSystemConfigurationFull()
2071 mode_lib->vba.MaxDispclk[v->soc.num_states - 1], in dml32_ModeSupportAndSystemConfigurationFull()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 169 .num_states = 5,
413 .num_states = 5,
619 for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) { in dcn31_update_bw_bounding_box_fpu()
652 dcn3_1_soc.num_states = clk_table->num_entries; in dcn31_update_bw_bounding_box_fpu()
712 dcn3_15_soc.num_states = clk_table->num_entries; in dcn315_update_bw_bounding_box_fpu()
758 for (closest_clk_lvl = 0, j = dcn3_16_soc.num_states - 1; j >= 0; j--) { in dcn316_update_bw_bounding_box_fpu()
792 dcn3_16_soc.num_states = clk_table->num_entries; in dcn316_update_bw_bounding_box_fpu()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 291 .num_states = 5,
402 .num_states = 5,
513 .num_states = 5,
764 .num_states = 8
1852 unsigned int num_states) in dcn20_update_bounding_box() argument
1860 if (num_states == 0) in dcn20_update_bounding_box()
1876 for (i = 0; i < num_states; i++) { in dcn20_update_bounding_box()
1907 bb->num_states = num_calculated_states; in dcn20_update_bounding_box()
1911 bb->clock_limits[num_calculated_states].state = bb->num_states; in dcn20_update_bounding_box()
1922 for (i = 0; i < bb->num_states; i++) { in dcn20_cap_soc_clocks()
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| H A D | dcn20_fpu.h | 61 unsigned int num_states);
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_socbb.h | 78 uint32_t num_states; member
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 1926 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) in dcn20_validate_apply_pipe_split_flags()
1931 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_validate_apply_pipe_split_flags()
2086 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_fast_validate_bw()
2160 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn20_fast_validate_bw()
2400 unsigned int num_states = 0; in init_soc_bounding_box() local
2407 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); in init_soc_bounding_box()
2422 if (clock_limits_available && uclk_states_available && num_states) { in init_soc_bounding_box()
2424 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states); in init_soc_bounding_box()
2624 if (loaded_bb->num_states == 1) { in dcn20_resource_construct()
2632 } else if (loaded_bb->num_states > 1) { in dcn20_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dm_pp_smu.h | 230 unsigned int *clock_values_in_khz, unsigned int *num_states);
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_structs.h | 187 unsigned int num_states; member
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| H A D | display_mode_vba.c | 376 for (i = 0; i < mode_lib->vba.soc.num_states; i++) in fetch_socbb_params()
394 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in fetch_socbb_params()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| H A D | dcn21_resource.c | 832 if (vlevel > context->bw_ctx.dml.soc.num_states) { in dcn21_fast_validate_bw()
845 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn21_fast_validate_bw()
937 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn21_fast_validate_bw()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| H A D | dcn301_resource.c | 1365 if (loaded_bb->num_states == 1) { in set_wm_ranges()
1373 } else if (loaded_bb->num_states > 1) { in set_wm_ranges()
1374 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) { in set_wm_ranges()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| H A D | dcn201_resource.c | 198 .num_states = 4,
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| /linux/drivers/gpu/drm/amd/pm/swsmu/inc/ |
| H A D | amdgpu_smu.h | 1034 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
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| /linux/sound/soc/ |
| H A D | soc-pcm.c | 62 int num_states) in snd_soc_dpcm_check_state() argument
75 for (i = 0; i < num_states; i++) { in snd_soc_dpcm_check_state()
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| /linux/include/net/ |
| H A D | ip_vs.h | 708 u16 num_states; member
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 1777 …_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn314_validate_bandwidth()
|