| /linux/arch/powerpc/kernel/ |
| H A D | rtas-proc.c | 508 int num_states = 0; in ppc_rtas_process_sensor() local
517 num_states = sizeof(key_switch) / sizeof(char *); in ppc_rtas_process_sensor()
518 if (state < num_states) { in ppc_rtas_process_sensor()
525 num_states = sizeof(enclosure_switch) / sizeof(char *); in ppc_rtas_process_sensor()
526 if (state < num_states) { in ppc_rtas_process_sensor()
538 num_states = sizeof(lid_status) / sizeof(char *); in ppc_rtas_process_sensor()
539 if (state < num_states) { in ppc_rtas_process_sensor()
546 num_states = sizeof(power_source) / sizeof(char *); in ppc_rtas_process_sensor()
547 if (state < num_states) { in ppc_rtas_process_sensor()
558 num_states = sizeof(battery_remaining) / sizeof(char *); in ppc_rtas_process_sensor()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_wrapper_fpu.c | 61 dml2_translate_soc_states(in_dc, out, in_dc->dml.soc.num_states); in initialize_dml2_soc_states()
107 s->mode_support_params.in_start_state_idx = dml2->v20.dml_core_ctx.states.num_states - 1; in pack_and_call_dml_mode_support_ex()
194 for (i = 0; i < dml2->v20.dml_core_ctx.states.num_states; i++) { in calculate_lowest_supported_state_for_temp_read()
199 for (j = 0; j < dml2->v20.dml_core_ctx.states.num_states; j++) { in calculate_lowest_supported_state_for_temp_read()
224 for (i = 0; i < dml2->v20.dml_core_ctx.states.num_states; i++) { in calculate_lowest_supported_state_for_temp_read()
469 (lowest_state_idx < dml2->v20.dml_core_ctx.states.num_states - 1)) { in dml2_validate_and_build_resource()
470 lowest_state_idx = dml2->v20.dml_core_ctx.states.num_states - 1; in dml2_validate_and_build_resource()
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| H A D | dml2_translation_helper.c | 362 p->in_states->num_states = 2; in dml2_init_soc_states()
398 p->in_states->num_states = 2; in dml2_init_soc_states()
435 p->in_states->num_states = 2; in dml2_init_soc_states()
472 for (i = 0; i < p->in_states->num_states; i++) { in dml2_init_soc_states()
527 if (dml2->config.bbox_overrides.clks_table.num_states) { in dml2_init_soc_states()
528 p->in_states->num_states = dml2->config.bbox_overrides.clks_table.num_states; in dml2_init_soc_states()
572 for (i = 0; i < p->in_states->num_states; i++) { in dml2_init_soc_states()
591 for (i = 0; i < p->in_states->num_states; i++) { in dml2_init_soc_states()
611 p->out_states->num_states = p->in_states->num_states; in dml2_init_soc_states()
720 void dml2_translate_soc_states(const struct dc *dc, struct soc_states_st *out, int num_states) in dml2_translate_soc_states() argument
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| H A D | display_mode_core_structs.h | 1267 dml_uint_t num_states; /// <brief num of soc pwr states member
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 1832 if ((unsigned int)vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1836 …alidate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING || vlevel == context->bw_ctx.dml.soc.num_states || in dcn30_internal_validate_bw()
1850 if ((unsigned int)vlevel < context->bw_ctx.dml.soc.num_states) { in dcn30_internal_validate_bw()
1860 if (vlevel == context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
2027 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; in dcn30_internal_validate_bw()
2249 …_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn30_validate_bandwidth()
2265 unsigned int num_states = 0; in dcn30_update_bw_bounding_box() local
2358 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()
2360 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box()
2361 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn30_update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_socbb.h | 78 uint32_t num_states; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.h | 61 unsigned int num_states);
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dm_pp_smu.h | 230 unsigned int *clock_values_in_khz, unsigned int *num_states);
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_structs.h | 187 unsigned int num_states; member
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| /linux/net/netfilter/ipvs/ |
| H A D | ip_vs_proto_udp.c | 451 .num_states = IP_VS_UDP_S_LAST,
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| H A D | ip_vs_proto_sctp.c | 570 .num_states = IP_VS_SCTP_S_LAST,
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| H A D | ip_vs_proto_tcp.c | 685 .num_states = IP_VS_TCP_S_LAST,
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| H A D | ip_vs_sync.c | 1018 if (state >= pp->num_states) { in ip_vs_process_message_v0()
1183 if (state >= pp->num_states) { in ip_vs_proc_sync_conn()
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| /linux/drivers/gpu/drm/amd/pm/ |
| H A D | amdgpu_dpm.c | 2013 unsigned int *num_states) in amdgpu_dpm_get_uclk_dpm_states() argument
2024 num_states); in amdgpu_dpm_get_uclk_dpm_states()
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| /linux/drivers/gpu/drm/amd/include/ |
| H A D | kgd_pp_interface.h | 526 unsigned int *num_states);
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| /linux/sound/soc/ |
| H A D | soc-pcm.c | 66 int num_states) in snd_soc_dpcm_check_state() argument
79 for (i = 0; i < num_states; i++) { in snd_soc_dpcm_check_state()
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| /linux/include/net/ |
| H A D | ip_vs.h | 722 u16 num_states; member
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 1906 …_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn314_validate_bandwidth()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.c | 1963 …_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn31_validate_bandwidth()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 1971 …_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dml1_validate()
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