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Searched refs:mul_shift (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/clk/at91/
H A Dclk-pll.c20 #define PLL_MUL(reg, layout) (((reg) >> (layout)->mul_shift) & \
90 ((pll->mul & layout->mul_mask) << layout->mul_shift)); in clk_pll_prepare()
361 .mul_shift = 16,
367 .mul_shift = 16,
373 .mul_shift = 16,
379 .mul_shift = 18,
H A Dclk-sam9x60-pll.c99 cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift; in sam9x60_frac_pll_set()
111 (frac->mul << core->layout->mul_shift) | in sam9x60_frac_pll_set()
269 cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift; in sam9x60_frac_pll_set_rate_chg()
276 (frac->mul << core->layout->mul_shift) | in sam9x60_frac_pll_set_rate_chg()
H A Dsam9x7.c150 .mul_shift = 24,
159 .mul_shift = 24,
H A Dpmc.h63 u8 mul_shift; member
H A Dsam9x60.c58 .mul_shift = 24,
H A Dsama7g5.c71 .mul_shift = 24,
H A Dsama7d65.c76 .mul_shift = 24,
/linux/drivers/clk/
H A Dclk-k230.c69 .mul_shift = _mul_shift, \
96 .mul_shift = _mul_shift, \
185 u32 mul_shift; member
2020 mul = (readl(rate_self->reg + clk->mul_reg_off) >> rate_self->mul_shift) in k230_clk_get_rate_mul()
2053 mul = (readl(rate_self->reg + clk->mul_reg_off) >> rate_self->mul_shift) in k230_clk_get_rate_mul_div()
2230 mul_reg &= ~(rate_self->mul_mask << rate_self->mul_shift); in k230_clk_set_rate_mul()
2231 mul_reg |= ((mul - 1) & rate_self->mul_mask) << (rate_self->mul_shift); in k230_clk_set_rate_mul()
2298 mul_reg &= ~(rate_self->mul_mask << rate_self->mul_shift); in k230_clk_set_rate_mul_div()
2299 mul_reg |= ((mul - 1) & rate_self->mul_mask) << (rate_self->mul_shift); in k230_clk_set_rate_mul_div()