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Searched refs:dml (Results 1 – 25 of 28) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/dml/
H A DMakefile47 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
48 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_ccflags)
49 CFLAGS_$(AMDDALPATH)/dc/dml/dcn10/dcn10_fpu.o := $(dml_ccflags)
50 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/dcn20_fpu.o := $(dml_ccflags)
51 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_ccflags) $(frame_warn_flag)
52 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20.o := $(dml_ccflags)
53 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20v2.o := $(dml_ccflags) $(frame_warn_flag)
54 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20v2.o := $(dml_ccflags)
55 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags) $(frame_warn_flag)
56 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_ccflags)
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/
H A Ddml2_top_soc15.c12 static void setup_unoptimized_display_config_with_meta(const struct dml2_instance *dml, struct disp… in setup_unoptimized_display_config_with_meta() argument
15 …out->stage1.min_clk_index_for_latency = dml->min_clk_table.dram_bw_table.num_entries - 1; //dml->m… in setup_unoptimized_display_config_with_meta()
18 static void setup_speculative_display_config_with_meta(const struct dml2_instance *dml, struct disp… in setup_speculative_display_config_with_meta() argument
20 (void)dml; in setup_speculative_display_config_with_meta()
67 l->test_mcache.calc_mcache_count_params.dml2_instance = params->dml; in dml2_top_optimization_test_function_mcache()
79 l->test_mcache.validate_admissibility_params.dml2_instance = params->dml; in dml2_top_optimization_test_function_mcache()
102 l->optimize_mcache.optimize_mcache_params.instance = &params->dml->pmo_instance; in dml2_top_optimization_optimize_function_mcache()
108 …optimize_success = params->dml->pmo_instance.optimize_dcc_mcache(&l->optimize_mcache.optimize_mcac… in dml2_top_optimization_optimize_function_mcache()
117 l->vmin.init_params.instance = &params->dml->pmo_instance; in dml2_top_optimization_init_function_vmin()
119 return params->dml->pmo_instance.init_for_vmin(&l->vmin.init_params); in dml2_top_optimization_init_function_vmin()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c459 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn31_update_soc_for_wm_a()
460 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A… in dcn31_update_soc_for_wm_a()
461 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_t… in dcn31_update_soc_for_wm_a()
471 …if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[context->bw_ctx.dml.vba.VoltageLevel][context->… in dcn315_update_soc_for_wm_a()
472 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latenc… in dcn315_update_soc_for_wm_a()
474 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn315_update_soc_for_wm_a()
475 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = in dcn315_update_soc_for_wm_a()
477 context->bw_ctx.dml.soc.sr_exit_time_us = in dcn315_update_soc_for_wm_a()
489 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp()
494 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) in dcn31_calculate_wm_and_dlg_fp()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c1039 …wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) *… in dcn20_fpu_set_wb_arb_params()
1040 …wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipe… in dcn20_fpu_set_wb_arb_params()
1085 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency; in decide_zstate_support()
1095 if (is_pwrseq0 && context->bw_ctx.dml.vba.StutterPeriod > 5000.0) in decide_zstate_support()
1153 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; in dcn20_calculate_dlg_params()
1154 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; in dcn20_calculate_dlg_params()
1155 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; in dcn20_calculate_dlg_params()
1156 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; in dcn20_calculate_dlg_params()
1161 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; in dcn20_calculate_dlg_params()
1162 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; in dcn20_calculate_dlg_params()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c189 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn32_build_wm_range_table_fpu()
190 double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us; in dcn32_build_wm_range_table_fpu()
191 double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us; in dcn32_build_wm_range_table_fpu()
192 double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us; in dcn32_build_wm_range_table_fpu()
197 …uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_m… in dcn32_build_wm_range_table_fpu()
282 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
284 …emp_clock_change_support = vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
290 …vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_suppor… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
291 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
298 …vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_suppor… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_translation_helper.c618 const struct _vcs_dpi_ip_params_st *in_ip_params = &in->dml.ip; in dml2_translate_ip_params()
687 const struct _vcs_dpi_soc_bounding_box_st *in_soc_params = &in->dml.soc; in dml2_translate_socbb_params()
725 out->state_array[i].dcfclk_mhz = dc->dml.soc.clock_limits[i].dcfclk_mhz; in dml2_translate_soc_states()
726 out->state_array[i].dispclk_mhz = dc->dml.soc.clock_limits[i].dispclk_mhz; in dml2_translate_soc_states()
727 out->state_array[i].dppclk_mhz = dc->dml.soc.clock_limits[i].dppclk_mhz; in dml2_translate_soc_states()
728 out->state_array[i].dram_speed_mts = dc->dml.soc.clock_limits[i].dram_speed_mts; in dml2_translate_soc_states()
729 out->state_array[i].dtbclk_mhz = dc->dml.soc.clock_limits[i].dtbclk_mhz; in dml2_translate_soc_states()
730 out->state_array[i].socclk_mhz = dc->dml.soc.clock_limits[i].socclk_mhz; in dml2_translate_soc_states()
731 out->state_array[i].fabricclk_mhz = dc->dml.soc.clock_limits[i].fabricclk_mhz; in dml2_translate_soc_states()
732 out->state_array[i].dscclk_mhz = dc->dml.soc.clock_limits[i].dscclk_mhz; in dml2_translate_soc_states()
[all …]
H A Ddml2_wrapper_fpu.c61 dml2_translate_soc_states(in_dc, out, in_dc->dml.soc.num_states); in initialize_dml2_soc_states()
497 context->bw_ctx.dml.vba.StutterPeriod = context->bw_ctx.dml2->v20.dml_core_ctx.mp.StutterPeriod; in dml2_validate_and_build_resource()
501 if (context->bw_ctx.dml.vba.StutterPeriod < in_dc->debug.minimum_z8_residency_time && in dml2_validate_and_build_resource()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c1414 struct display_mode_lib *dml = &context->bw_ctx.dml; in dcn30_set_mcif_arb_params() local
1441 dcn30_fpu_set_mcif_arb_params(wb_arb_params, dml, pipes, pipe_cnt, j); in dcn30_set_mcif_arb_params()
1673 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn30_internal_validate_bw()
1681 context->bw_ctx.dml.vba.maxMpcComb = 0; in dcn30_internal_validate_bw()
1682 context->bw_ctx.dml.vba.VoltageLevel = 0; in dcn30_internal_validate_bw()
1683 context->bw_ctx.dml.vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive; in dcn30_internal_validate_bw()
1692 dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_internal_validate_bw()
1700 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = in dcn30_internal_validate_bw()
1702 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_internal_validate_bw()
1704 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/
H A DMakefile25 DC_LIBS = basics bios dml clk_mgr dce gpio hwss irq link dsc resource optc dpp hubbub dccg hubp dio…
38 DC_LIBS += dml
H A Ddc.h1826 struct display_mode_lib dml; member
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c828 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = in dcn21_fast_validate_bw()
830 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
832 if (vlevel > context->bw_ctx.dml.soc.num_states) { in dcn21_fast_validate_bw()
842 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = in dcn21_fast_validate_bw()
844 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
845 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn21_fast_validate_bw()
857 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn21_fast_validate_bw()
887 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
911 …dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe… in dcn21_fast_validate_bw()
915 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c1871 struct vba_vars_st *v = &context->bw_ctx.dml.vba; in dcn20_validate_apply_pipe_split_flags()
1926 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) in dcn20_validate_apply_pipe_split_flags()
1931 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_validate_apply_pipe_split_flags()
2084 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn20_fast_validate_bw()
2086 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_fast_validate_bw()
2104 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn20_fast_validate_bw()
2123 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) in dcn20_fast_validate_bw()
2133 …dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe… in dcn20_fast_validate_bw()
2137 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn20_fast_validate_bw()
2160 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn20_fast_validate_bw()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/
H A Ddcn315_resource.c1705 …const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MI… in dcn315_populate_dml_pipes_from_context()
1738 &context->bw_ctx.dml.soc, timing->pix_clk_100hz, bpp, DCN3_15_CRB_SEGMENT_SIZE_KB); in dcn315_populate_dml_pipes_from_context()
1742 …ired = split_required || timing->pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc); in dcn315_populate_dml_pipes_from_context()
1791 …t_required = pipe->stream->timing.pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc) in dcn315_populate_dml_pipes_from_context()
1816 context->bw_ctx.dml.ip.det_buffer_size_kbytes = in dcn315_populate_dml_pipes_from_context()
1818 if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_15_MAX_DET_SIZE) in dcn315_populate_dml_pipes_from_context()
1819 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_15_MAX_DET_SIZE; in dcn315_populate_dml_pipes_from_context()
1824 context->bw_ctx.dml.ip.det_buffer_size_kbytes = in dcn315_populate_dml_pipes_from_context()
1828 && pipe->stream->timing.pix_clk_100hz < dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) { in dcn315_populate_dml_pipes_from_context()
1830 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn315_populate_dml_pipes_from_context()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c1650 …const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_16_MI… in dcn316_populate_dml_pipes_from_context()
1700 context->bw_ctx.dml.ip.det_buffer_size_kbytes = in dcn316_populate_dml_pipes_from_context()
1702 if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_16_MAX_DET_SIZE) in dcn316_populate_dml_pipes_from_context()
1703 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_16_MAX_DET_SIZE; in dcn316_populate_dml_pipes_from_context()
1704 ASSERT(context->bw_ctx.dml.ip.det_buffer_size_kbytes >= DCN3_16_DEFAULT_DET_SIZE); in dcn316_populate_dml_pipes_from_context()
1708 context->bw_ctx.dml.ip.det_buffer_size_kbytes = in dcn316_populate_dml_pipes_from_context()
1711 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn316_populate_dml_pipes_from_context()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c1734 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE; in dcn31_populate_dml_pipes_from_context()
1739 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn31_populate_dml_pipes_from_context()
1744 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64; in dcn31_populate_dml_pipes_from_context()
1746 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn31_populate_dml_pipes_from_context()
1755 return context->bw_ctx.dml.ip.det_buffer_size_kbytes; in dcn31_get_det_buffer_size()
1835 …dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_st… in dcn31_validate_bandwidth()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c907 ctx->dc->dml.ip.det_buffer_size_kbytes, in dcn32_hubbub_create()
908 ctx->dc->dml.ip.pixel_chunk_size_kbytes, in dcn32_hubbub_create()
909 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); in dcn32_hubbub_create()
1801 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; in dml1_validate()
1841 …dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_st… in dml1_validate()
2060 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = false; in dcn32_populate_dml_pipes_from_context()
2062 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; in dcn32_populate_dml_pipes_from_context()
2402 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); in dcn32_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c896 ctx->dc->dml.ip.det_buffer_size_kbytes, in dcn321_hubbub_create()
897 ctx->dc->dml.ip.pixel_chunk_size_kbytes, in dcn321_hubbub_create()
898 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); in dcn321_hubbub_create()
1895 dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32); in dcn321_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/
H A Ddcn10_resource.c1511 dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1); in dcn10_resource_construct()
1682 dc->dml.ip.max_num_dpp = pool->base.pipe_count; in dcn10_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c1777 …dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_st… in dcn314_validate_bandwidth()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c1232 dml_init_instance(&dc->dml, &dcn201_soc, &dcn201_ip, DML_PROJECT_DCN201); in dcn201_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.c1326 dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); in dcn303_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/
H A Ddcn302_resource.c1394 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); in dcn302_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/
H A Ddcn301_resource.c1605 dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30); in dcn301_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c2020 dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31); in dcn351_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c2048 dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31); in dcn35_resource_construct()

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