Searched refs:div0 (Results 1 – 2 of 2) sorted by relevance
213 int div0, div1; in cgem_set_ref_clk() local222 div0 = (io_pll_frequency + div1 * frequency / 2) / in cgem_set_ref_clk()224 if (div0 > 0 && div0 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_MAX && in cgem_set_ref_clk()225 ((io_pll_frequency / div0 / div1) + 500) / 1000 == in cgem_set_ref_clk()241 (div0 << ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_SHIFT) | in cgem_set_ref_clk()314 int div0, div1; in zy7_pl_fclk_set_freq() local344 div0 = (base_frequency + div1 * frequency / 2) / in zy7_pl_fclk_set_freq()346 if (div0 > 0 && div0 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX && in zy7_pl_fclk_set_freq()347 ((base_frequency / div0 / div1) + 500) / 1000 == in zy7_pl_fclk_set_freq()365 (div0 << ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_SHIFT); in zy7_pl_fclk_set_freq()[all …]
1150 "div0.s\t$r, $s", []>, Requires<[HasSingleFloat]> {