169 	unsigned long div0;  in exynos_set_safe_div()  local
171 	div0 = readl(base + regs->div_cpu0);  in exynos_set_safe_div()
172 	div0 = (div0 & ~mask) | (div & mask);  in exynos_set_safe_div()
173 	writel(div0, base + regs->div_cpu0);  in exynos_set_safe_div()
203 	unsigned long div0, div1 = 0, mux_reg;  in exynos_cpuclk_pre_rate_change()  local
220 	div0 = cfg_data->div0;  in exynos_cpuclk_pre_rate_change()
252 		div0 |= alt_div;  in exynos_cpuclk_pre_rate_change()
261 	writel(div0, base + regs->div_cpu0);  in exynos_cpuclk_pre_rate_change()
302 		div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK);  in exynos_cpuclk_post_rate_change()
330 	unsigned long div0, div1 = 0, mux_reg;  in exynos5433_cpuclk_pre_rate_change()  local
346 	div0 = cfg_data->div0;  in exynos5433_cpuclk_pre_rate_change()
365 		div0 |= alt_div;  in exynos5433_cpuclk_pre_rate_change()
374 	writel(div0, base + regs->div_cpu0);  in exynos5433_cpuclk_pre_rate_change()
526 		unsigned long div = (cfg_data->div0 >> shifts[i]) & 0xf;  in exynos850_cpuclk_pre_rate_change()