| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| H A D | dcn401_clk_mgr.c | 82 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_socclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
86 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_memclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
90 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
94 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
98 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dppclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
105 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
109 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
176 for (i = 0; i < *num_levels && i < ARRAY_SIZE(clk_mgr->base.bw_params->clk_table.entries); i++) { in dcn401_init_single_clock()
178 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); in dcn401_init_single_clock()
185 uint16_t min_uclk_mhz = clk_mgr->bw_params->clk_table.entries[0].memclk_mhz; in dcn401_build_wm_range_table()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.c | 98 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); in dcn3_init_single_clock()
119 if (!clk_mgr_base->bw_params) in dcn3_init_clocks()
134 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn3_init_clocks()
140 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, in dcn3_init_clocks()
145 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, in dcn3_init_clocks()
151 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, in dcn3_init_clocks()
156 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz, in dcn3_init_clocks()
161 &clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz, in dcn3_init_clocks()
254 if ((new_clocks->dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) != in dcn3_update_clocks()
255 (clk_mgr_base->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)) in dcn3_update_clocks()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 864 static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn35_watermarks *… in dcn35_build_watermark_ranges() argument
872 if (!bw_params->wm_table.entries[i].valid) in dcn35_build_watermark_ranges()
875 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn35_build_watermark_ranges()
876 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn35_build_watermark_ranges()
887 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn35_build_watermark_ranges()
890 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn35_build_watermark_ranges()
933 dcn35_build_watermark_ranges(clk_mgr_base->bw_params, table); in dcn35_notify_wm_ranges()
1022 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; in dcn35_clk_mgr_helper_populate_bw_params() local
1023 …struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entri… in dcn35_clk_mgr_helper_populate_bw_params()
1083 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--) in dcn35_clk_mgr_helper_populate_bw_params()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 151 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); in dcn32_init_single_clock()
169 if (!clk_mgr_base->bw_params) in dcn32_init_clocks()
172 num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk; in dcn32_init_clocks()
192 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn32_init_clocks()
194 …clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PP… in dcn32_init_clocks()
198 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, in dcn32_init_clocks()
200 …clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PP… in dcn32_init_clocks()
205 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, in dcn32_init_clocks()
207 clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = in dcn32_init_clocks()
213 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, in dcn32_init_clocks()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 454 static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ra… in build_watermark_ranges() argument
462 if (!bw_params->wm_table.entries[i].valid) in build_watermark_ranges()
465 ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst; in build_watermark_ranges()
466 ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type; in build_watermark_ranges()
477 …ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcf… in build_watermark_ranges()
479 …ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_… in build_watermark_ranges()
519 build_watermark_ranges(clk_mgr_base->bw_params, &clk_mgr_base->ranges); in rn_notify_wm_ranges()
640 static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks… in rn_clk_mgr_helper_populate_bw_params() argument
664 bw_params->clk_table.num_entries = j + 1; in rn_clk_mgr_helper_populate_bw_params()
666 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { in rn_clk_mgr_helper_populate_bw_params()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 458 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn31_update_soc_for_wm_a()
459 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn31_update_soc_for_wm_a()
460 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A… in dcn31_update_soc_for_wm_a()
461 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_t… in dcn31_update_soc_for_wm_a()
469 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn315_update_soc_for_wm_a()
474 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn315_update_soc_for_wm_a()
476 dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us; in dcn315_update_soc_for_wm_a()
478 dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us; in dcn315_update_soc_for_wm_a()
590 void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn31_update_bw_bounding_box() argument
593 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn31_update_bw_bounding_box()
[all …]
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| /linux/drivers/media/tuners/ |
| H A D | tda18212.c | 36 static const u8 bw_params[][3] = { in tda18212_set_params() local
115 ret = regmap_write(dev->regmap, 0x23, bw_params[i][2]); in tda18212_set_params()
123 ret = regmap_write(dev->regmap, 0x0f, bw_params[i][0]); in tda18212_set_params()
128 buf[1] = bw_params[i][1]; in tda18212_set_params()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 2097 void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn30_update_bw_bounding_box() argument
2122 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn30_update_bw_bounding_box()
2125 if (bw_params->clk_table.entries[i].dcfclk_mhz > dcn30_bb_max_clk.max_dcfclk_mhz) in dcn30_update_bw_bounding_box()
2126 dcn30_bb_max_clk.max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn30_update_bw_bounding_box()
2127 if (bw_params->clk_table.entries[i].dispclk_mhz > dcn30_bb_max_clk.max_dispclk_mhz) in dcn30_update_bw_bounding_box()
2128 dcn30_bb_max_clk.max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn30_update_bw_bounding_box()
2129 if (bw_params->clk_table.entries[i].dppclk_mhz > dcn30_bb_max_clk.max_dppclk_mhz) in dcn30_update_bw_bounding_box()
2130 dcn30_bb_max_clk.max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn30_update_bw_bounding_box()
2131 if (bw_params->clk_table.entries[i].phyclk_mhz > dcn30_bb_max_clk.max_phyclk_mhz) in dcn30_update_bw_bounding_box()
2132 dcn30_bb_max_clk.max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn30_update_bw_bounding_box()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn321/ |
| H A D | dcn321_fpu.h | 32 void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn303/ |
| H A D | dcn303_fpu.h | 29 void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn302/ |
| H A D | dcn302_fpu.h | 30 void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| H A D | dcn302_resource.h | 36 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| H A D | dcn303_resource.h | 36 void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.h | 30 void dcn301_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| H A D | dcn32_hwseq.c | 761 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; in dcn32_initialize_min_clocks()
762 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; in dcn32_initialize_min_clocks()
763 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; in dcn32_initialize_min_clocks()
764 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000; in dcn32_initialize_min_clocks()
765 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; in dcn32_initialize_min_clocks()
769 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000; in dcn32_initialize_min_clocks()
1012 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params); in dcn32_init_hw()
1809 if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && in dcn32_prepare_bandwidth()
1810 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) in dcn32_prepare_bandwidth()
1811 …r->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_pa… in dcn32_prepare_bandwidth()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| H A D | dcn351_fpu.c | 262 struct clk_bw_params *bw_params) in dcn351_update_bw_bounding_box_fpu() argument
266 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn351_update_bw_bounding_box_fpu()
276 dcn3_51_soc.num_chans = bw_params->num_channels; in dcn351_update_bw_bounding_box_fpu()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| H A D | dcn35_fpu.c | 228 struct clk_bw_params *bw_params) in dcn35_update_bw_bounding_box_fpu() argument
232 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn35_update_bw_bounding_box_fpu()
242 dcn3_5_soc.num_chans = bw_params->num_channels; in dcn35_update_bw_bounding_box_fpu()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 63 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; in dcn401_initialize_min_clocks()
64 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; in dcn401_initialize_min_clocks()
65 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; in dcn401_initialize_min_clocks()
66 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000; in dcn401_initialize_min_clocks()
68 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000; in dcn401_initialize_min_clocks()
81 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; in dcn401_initialize_min_clocks()
370 dc->clk_mgr->bw_params); in dcn401_init_hw()
1390 if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && in dcn401_prepare_bandwidth()
1391 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) in dcn401_prepare_bandwidth()
1392 …r->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_pa… in dcn401_prepare_bandwidth()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| H A D | dcn401_resource.c | 1646 static void dcn401_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn401_update_bw_bounding_box() argument
1649 if (bw_params->num_channels > 0) { in dcn401_update_bw_bounding_box()
1651 dc, bw_params->num_channels) * in dcn401_update_bw_bounding_box()
1798 …for (int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; … in dcn401_get_power_profile()
1799 if (context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz == 0 || in dcn401_get_power_profile()
1800 uclk_mhz < context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz) in dcn401_get_power_profile()
1802 if (uclk_mhz > context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz) in dcn401_get_power_profile()
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| /linux/drivers/media/dvb-frontends/ |
| H A D | rtl2832.c | 411 static u8 bw_params[3][32] = { in rtl2832_set_frontend() local
477 for (j = 0; j < sizeof(bw_params[0]); j++) { in rtl2832_set_frontend()
479 0x11c + j, &bw_params[i][j], 1); in rtl2832_set_frontend()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | clk_mgr.h | 356 struct clk_bw_params *bw_params; member
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| H A D | dcn30_hwseq.c | 1199 if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && in dcn30_prepare_bandwidth()
1200 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) in dcn30_prepare_bandwidth()
1201 …r->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_pa… in dcn30_prepare_bandwidth()
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| /linux/drivers/net/ethernet/broadcom/bnx2x/ |
| H A D | bnx2x_link.h | 506 struct bnx2x_ets_bw_params bw_params; member
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | core_types.h | 191 struct clk_bw_params *bw_params);
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_helpers.c | 1351 clk_mgr->bw_params->dc_mode_softmax_memclk : clk_mgr->bw_params->max_memclk_mhz; in dm_helpers_dp_handle_test_pattern_request()
|