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Searched refs:bridges (Results 1 – 25 of 56) sorted by relevance

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/linux/drivers/soc/tegra/cbb/
H A Dtegra194-cbb.c172 struct tegra194_axi2apb_bridge *bridges; member
1893 status = tegra194_axi2apb_status(cbb->bridges[i].base); in print_errlog0()
2200 if (priv->bridges) { in tegra194_cbb_get_bridges()
2202 cbb->bridges = priv->bridges; in tegra194_cbb_get_bridges()
2209 if (!cbb->bridges) { in tegra194_cbb_get_bridges()
2212 cbb->bridges = devm_kcalloc(cbb->base.dev, cbb->num_bridges, in tegra194_cbb_get_bridges()
2213 sizeof(*cbb->bridges), GFP_KERNEL); in tegra194_cbb_get_bridges()
2214 if (!cbb->bridges) in tegra194_cbb_get_bridges()
2218 err = of_address_to_resource(np, i, &cbb->bridges[i].res); in tegra194_cbb_get_bridges()
2222 cbb->bridges[i].base = devm_ioremap_resource(cbb->base.dev, in tegra194_cbb_get_bridges()
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/linux/Documentation/driver-api/fpga/
H A Dfpga-programming.rst12 the FPGA manager and bridges. It will:
16 * build a list of FPGA bridges if a method has been specified to do so
17 * disable the bridges
19 * re-enable the bridges
31 bridges to control during programming or it has a pointer to a function that
H A Dintro.rst50 bridges as reconfigurable regions. A region may refer to the whole
/linux/Documentation/driver-api/cxl/platform/example-configurations/
H A Dhb-interleave.rst6 This system has a single socket with two CXL host bridges. Each host bridge
13 * This SRAT describes one node for both host bridges.
/linux/Documentation/ABI/testing/
H A Dsysfs-devices-pci-host-bridge6 controllers may also parent host bridges. The DDDD:BB format
10 for emulated host-bridges.
H A Dsysfs-class-rapidio3 On-chip RapidIO controllers and PCIe-to-RapidIO bridges
/linux/Documentation/i2c/busses/
H A Di2c-sis96x.rst11 Any combination of these host bridges:
14 and these south bridges:
H A Di2c-ali1563.rst24 the i2c controller found in the Intel 801 south bridges.
H A Di2c-ali1535.rst25 M15x3 South bridges also produced by Acer Labs Inc. Some of the registers
H A Di2c-viapro.rst47 supported VIA south bridges.
/linux/Documentation/driver-api/cxl/platform/acpi/
H A Ddsdt.rst9 This table's UIDs for CXL devices - specifically host bridges, must be
/linux/Documentation/driver-api/cxl/linux/example-configurations/
H A Dhb-interleave.rst11 * The CXL root is configured to interleave across the two host bridges.
212 The next chunk shows the two CXL host bridges without attached endpoints.
H A Dmulti-interleave.rst11 * The CXL root is configured to interleave across the two host bridges.
288 The next chunk shows the two CXL host bridges without attached endpoints.
H A Dsingle-device.rst145 The next chunk shows the three CXL host bridges without attached endpoints.
/linux/Documentation/PCI/
H A Dacpi-info.rst4 ACPI considerations for PCI host bridges
11 host bridges, so the ACPI namespace must describe each host bridge, the
44 PCI host bridges are PNP0A03 or PNP0A08 devices. Their _CRS should
93 bridges [8]. Since MCFG is a static table and can't be updated by hotplug,
/linux/drivers/net/ethernet/mellanox/mlx5/core/esw/
H A Dbridge.h19 struct list_head bridges; member
H A Dbridge.c869 list_add(&bridge->list, &br_offloads->bridges); in mlx5_esw_bridge_create()
902 if (list_empty(&br_offloads->bridges)) in mlx5_esw_bridge_put()
913 list_for_each_entry(bridge, &br_offloads->bridges, list) { in mlx5_esw_bridge_lookup()
928 if (IS_ERR(bridge) && list_empty(&br_offloads->bridges)) in mlx5_esw_bridge_lookup()
1833 list_for_each_entry(bridge, &br_offloads->bridges, list) { in mlx5_esw_bridge_update()
1917 WARN_ONCE(!list_empty(&br_offloads->bridges), in mlx5_esw_bridge_flush()
1931 INIT_LIST_HEAD(&br_offloads->bridges); in mlx5_esw_bridge_init()
/linux/Documentation/driver-api/cxl/linux/
H A Dcxl-driver.rst27 Here is an example from a single-socket system with 4 host bridges. Two host
28 bridges have a single memory device attached, and the devices are interleaved
186 In our example described above, there are four host bridges attached to the
187 root, and two of the host bridges have one endpoint attached.
325 host bridges).
379 accesses over two host bridges. Each host bridge has a decoder which routes
504 attached to 4 host bridges, linux expects the following ways/granularity
/linux/Documentation/networking/dsa/
H A Db53.rst88 # add ports to bridges
168 # add ports to bridges
/linux/drivers/net/dsa/mxl862xx/
H A Dmxl862xx.c426 bridge_id = dp->bridge ? priv->bridges[dp->bridge->num] : p->fid; in mxl862xx_set_bridge_port()
606 u16 fw_id = priv->bridges[bridge->num]; in mxl862xx_free_bridge()
619 priv->bridges[bridge->num] = 0; in mxl862xx_free_bridge()
1281 if (!priv->bridges[bridge.num]) { in mxl862xx_port_bridge_join()
1286 priv->bridges[bridge.num] = ret; in mxl862xx_port_bridge_join()
1443 if (!priv->bridges[db.bridge.num]) in mxl862xx_get_fid()
1445 return priv->bridges[db.bridge.num]; in mxl862xx_get_fid()
/linux/net/hsr/
H A DKconfig28 can have Singly Attached Nodes (SAN) such as PC, printer, bridges
/linux/drivers/w1/masters/
H A DKconfig33 Say Y here if you want to have a driver for DS2490 based USB <-> W1 bridges,
/linux/drivers/firmware/efi/
H A DKconfig198 bool "Clear Busmaster bit on PCI bridges during ExitBootServices()"
200 Disable the busmaster bit in the control register on all PCI bridges
210 PCI bridges before ExitBootServices() is called. This will prevent
/linux/Documentation/w1/masters/
H A Dds2490.rst16 which allows to build USB <-> W1 bridges.
/linux/Documentation/hwmon/
H A Dlm83.rst83 north and south bridges, but this couldn't be confirmed.

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