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Searched refs:VMID (Results 1 – 25 of 26) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn21/
H A Ddcn21_hubp.h91 HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v7.c51 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue); in lock_srbm()
561 return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in read_vmid_from_vmfault_reg()
H A Dvid.h72 #define VMID(x) ((x) << 4) macro
H A Dgfx_v11_0.c2588 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_me_cache()
2632 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_pfp_cache()
2707 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_pfp_cache_rs64()
2788 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_pfp_cache_rs64()
2829 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_me_cache_rs64()
2911 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_me_cache_rs64()
2947 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_mec_cache_rs64()
2953 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_mec_cache_rs64()
3322 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3403 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
[all …]
H A Damdgpu_amdkfd_gfx_v10.c907 VMID, in kgd_gfx_v10_set_address_watch()
921 VMID, in kgd_gfx_v10_set_address_watch()
H A Dsoc24.c108 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); in soc24_grbm_select()
H A Dumsch_mm_v4_0.c84 data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, VMID, 0); in umsch_mm_v4_0_load_microcode()
H A Damdgpu_amdkfd_gfx_v8.c45 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue); in lock_srbm()
H A Dgfx_v12_0.c2449 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2503 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2593 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2648 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2903 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); in gfx_v12_0_cp_compute_load_microcode_rs64()
2909 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); in gfx_v12_0_cp_compute_load_microcode_rs64()
3020 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); in gfx_v12_0_gfx_mqd_init()
3027 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); in gfx_v12_0_gfx_mqd_init()
3233 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in gfx_v12_0_compute_mqd_init()
H A Dmes_v11_0.c1454 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in mes_v11_0_mqd_init()
1530 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); in mes_v11_0_queue_init_register()
1545 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); in mes_v11_0_queue_init_register()
H A Dmes_v12_1.c1299 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in mes_v12_1_mqd_init()
1383 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); in mes_v12_1_queue_init_register()
1398 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); in mes_v12_1_queue_init_register()
H A Dmes_v12_0.c1523 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in mes_v12_0_mqd_init()
1606 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); in mes_v12_0_queue_init_register()
1621 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); in mes_v12_0_queue_init_register()
H A Dsoc21.c276 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); in soc21_grbm_select()
H A Damdgpu_amdkfd_gfx_v9.c837 VMID, in kgd_gfx_v9_set_address_watch()
H A Dgfx_v12_1.c2333 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); in gfx_v12_1_xcc_cp_compute_load_microcode_rs64()
2339 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); in gfx_v12_1_xcc_cp_compute_load_microcode_rs64()
2497 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in gfx_v12_1_compute_mqd_init()
H A Dgfx_v10_0.c6169 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); in gfx_v10_0_cp_gfx_load_pfp_microcode()
6247 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); in gfx_v10_0_cp_gfx_load_ce_microcode()
6324 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); in gfx_v10_0_cp_gfx_load_me_microcode()
6791 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); in gfx_v10_0_gfx_mqd_init()
6798 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); in gfx_v10_0_gfx_mqd_init()
6974 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in gfx_v10_0_compute_mqd_init()
H A Dgfx_v9_4_3.c1708 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); in gfx_v9_4_3_xcc_cp_compute_load_microcode()
1828 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in gfx_v9_4_3_xcc_mqd_init()
H A Dgfx_v9_0.c3501 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); in gfx_v9_0_cp_compute_load_microcode()
3619 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in gfx_v9_0_mqd_init()
/linux/Documentation/trace/coresight/
H A Dcoresight-etm4x-reference.rst461 Automatically clears masked bytes to 0 in VMID value registers.
466 Where mN represents a byte mask value for VMID comparator N.
468 VMID comparators.
475 Number of VMID comparators
H A Dcoresight-cpu-debug.rst188 …esight-cpu-debug 850000.debug: EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
193 …esight-cpu-debug 852000.debug: EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
/linux/drivers/gpu/drm/radeon/
H A Dcik_sdma.c961 radeon_ring_write(ring, VMID(vm_id)); in cik_dma_vm_flush()
981 radeon_ring_write(ring, VMID(0)); in cik_dma_vm_flush()
H A Dnid.h61 #define VMID(x) (((x) & 0x7) << 0) macro
H A Dcikd.h447 #define VMID(x) ((x) << 4) macro
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dsmu8_smumgr.c200 tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); in smu8_load_mec_firmware()
/linux/drivers/iommu/
H A Dmsm_iommu_hw-8xxx.h191 #define SET_VMID(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), VMID, v)
309 #define GET_VMID(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), VMID)
919 #define VMID (VMID_MASK << VMID_SHIFT) macro

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