Home
last modified time | relevance | path

Searched refs:RREG32 (Results 1 – 25 of 118) sorted by relevance

12345

/linux/drivers/gpu/drm/radeon/
H A Dradeon_legacy_encoders.c67 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_lvds_update()
95 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN); in radeon_legacy_lvds_update()
98 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); in radeon_legacy_lvds_update()
103 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); in radeon_legacy_lvds_update()
198 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); in radeon_legacy_lvds_mode_set()
201 lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); in radeon_legacy_lvds_mode_set()
208 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_lvds_mode_set()
219 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_lvds_mode_set()
289 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> in radeon_legacy_get_backlight_level()
361 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> in radeon_legacy_backlight_get_brightness()
[all …]
H A Dradeon_i2c.c124 temp = RREG32(rec->mask_clk_reg); in pre_xfer()
130 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; in pre_xfer()
133 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; in pre_xfer()
137 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; in pre_xfer()
140 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; in pre_xfer()
144 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; in pre_xfer()
146 temp = RREG32(rec->mask_clk_reg); in pre_xfer()
148 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; in pre_xfer()
150 temp = RREG32(rec->mask_data_reg); in pre_xfer()
163 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; in post_xfer()
[all …]
H A Dvce_v2_0.c44 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
48 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
52 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
58 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
63 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
68 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
78 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_dyn_cg()
88 orig = tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_dyn_cg()
94 orig = tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_dyn_cg()
135 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v2_0_init_cg()
[all …]
H A Dvce_v1_0.c64 return RREG32(VCE_RB_RPTR); in vce_v1_0_get_rptr()
66 return RREG32(VCE_RB_RPTR2); in vce_v1_0_get_rptr()
81 return RREG32(VCE_RB_WPTR); in vce_v1_0_get_wptr()
83 return RREG32(VCE_RB_WPTR2); in vce_v1_0_get_wptr()
108 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v1_0_enable_mgcg()
112 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v1_0_enable_mgcg()
117 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v1_0_enable_mgcg()
121 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v1_0_enable_mgcg()
125 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v1_0_enable_mgcg()
130 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v1_0_enable_mgcg()
[all …]
H A Drs600.c64 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) in avivo_is_in_vblank()
74 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving()
75 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving()
98 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) in avivo_wait_for_vblank()
123 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rs600_page_flip()
144 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rs600_page_flip()
160 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rs600_page_flip_pending()
238 tmp = RREG32(voltage->gpio.reg); in rs600_pm_misc()
247 tmp = RREG32(voltage->gpio.reg); in rs600_pm_misc()
333 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); in rs600_pm_prepare()
[all …]
H A Drv730_dpm.c200 RREG32(CG_SPLL_FUNC_CNTL); in rv730_read_clock_registers()
202 RREG32(CG_SPLL_FUNC_CNTL_2); in rv730_read_clock_registers()
204 RREG32(CG_SPLL_FUNC_CNTL_3); in rv730_read_clock_registers()
206 RREG32(CG_SPLL_SPREAD_SPECTRUM); in rv730_read_clock_registers()
208 RREG32(CG_SPLL_SPREAD_SPECTRUM_2); in rv730_read_clock_registers()
211 RREG32(TCI_MCLK_PWRMGT_CNTL); in rv730_read_clock_registers()
213 RREG32(TCI_DLL_CNTL); in rv730_read_clock_registers()
215 RREG32(CG_MPLL_FUNC_CNTL); in rv730_read_clock_registers()
217 RREG32(CG_MPLL_FUNC_CNTL_2); in rv730_read_clock_registers()
219 RREG32(CG_MPLL_FUNC_CNTL_3); in rv730_read_clock_registers()
[all …]
H A Dr600.c127 r = RREG32(R600_RCU_DATA); in r600_rcu_rreg()
149 r = RREG32(R600_UVD_CTX_DATA); in r600_uvd_ctx_rreg()
183 *val = RREG32(reg); in r600_get_allowed_info_register()
352 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> in rv6xx_get_temp()
797 if (RREG32(GRBM_STATUS) & GUI_ACTIVE) in r600_gui_idle()
811 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
815 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
819 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
823 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
828 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
[all …]
H A Dr100.c81 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) in r100_is_in_vblank()
86 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) in r100_is_in_vblank()
98 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
99 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
101 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
102 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
126 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN)) in r100_wait_for_vblank()
129 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN)) in r100_wait_for_vblank()
185 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) in r100_page_flip()
211 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & in r100_page_flip_pending()
[all …]
H A Drs400.c157 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; in rs400_gart_enable()
161 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; in rs400_gart_enable()
248 tmp = RREG32(RADEON_MC_STATUS); in rs400_mc_wait_for_idle()
277 RREG32(RADEON_MC_STATUS)); in rs400_gpu_init()
291 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; in rs400_mc_init()
305 r = RREG32(RS480_NB_MC_DATA); in rs400_mc_rreg()
328 tmp = RREG32(RADEON_HOST_PATH_CNTL); in rs400_debugfs_gart_info_show()
330 tmp = RREG32(RADEON_BUS_CNTL); in rs400_debugfs_gart_info_show()
343 tmp = RREG32(RS690_HDP_FB_LOCATION); in rs400_debugfs_gart_info_show()
346 tmp = RREG32(RADEON_AGP_BASE); in rs400_debugfs_gart_info_show()
[all …]
H A Dr420.c104 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); in r420_pipes_init()
140 tmp = RREG32(R300_DST_PIPE_CONFIG); in r420_pipes_init()
144 RREG32(R300_RB2D_DSTCACHE_MODE) | in r420_pipes_init()
153 tmp = RREG32(RV530_GB_PIPE_SELECT2); in r420_pipes_init()
172 r = RREG32(R_0001FC_MC_IND_DATA); in r420_mc_rreg()
286 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in r420_startup()
318 RREG32(R_000E40_RBBM_STATUS), in r420_resume()
319 RREG32(R_0007C0_CP_STAT)); in r420_resume()
409 RREG32(R_000E40_RBBM_STATUS), in r420_init()
410 RREG32(R_0007C0_CP_STAT)); in r420_init()
[all …]
H A Dni.c54 r = RREG32(TN_SMC_IND_DATA_0); in tn_smc_rreg()
652 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT; in ni_mc_load_microcode()
653 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; in ni_mc_load_microcode()
677 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD) in ni_mc_load_microcode()
847 *val = RREG32(reg); in cayman_get_allowed_info_register()
993 RREG32(MC_SHARED_CHMAP); in cayman_gpu_init()
994 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); in cayman_gpu_init()
1071 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16; in cayman_gpu_init()
1091 simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16; in cayman_gpu_init()
1140 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG); in cayman_gpu_init()
[all …]
H A Drv740_dpm.c292 RREG32(CG_SPLL_FUNC_CNTL); in rv740_read_clock_registers()
294 RREG32(CG_SPLL_FUNC_CNTL_2); in rv740_read_clock_registers()
296 RREG32(CG_SPLL_FUNC_CNTL_3); in rv740_read_clock_registers()
298 RREG32(CG_SPLL_SPREAD_SPECTRUM); in rv740_read_clock_registers()
300 RREG32(CG_SPLL_SPREAD_SPECTRUM_2); in rv740_read_clock_registers()
303 RREG32(MPLL_AD_FUNC_CNTL); in rv740_read_clock_registers()
305 RREG32(MPLL_AD_FUNC_CNTL_2); in rv740_read_clock_registers()
307 RREG32(MPLL_DQ_FUNC_CNTL); in rv740_read_clock_registers()
309 RREG32(MPLL_DQ_FUNC_CNTL_2); in rv740_read_clock_registers()
311 RREG32(MCLK_PWRMGT_CNTL); in rv740_read_clock_registers()
[all …]
H A Dsi_smc.c86 original_data = RREG32(SMC_IND_DATA_0); in si_copy_bytes_to_smc()
126 RREG32(CB_CGTT_SCLK_CTRL); in si_reset_smc()
127 RREG32(CB_CGTT_SCLK_CTRL); in si_reset_smc()
128 RREG32(CB_CGTT_SCLK_CTRL); in si_reset_smc()
129 RREG32(CB_CGTT_SCLK_CTRL); in si_reset_smc()
183 tmp = RREG32(SMC_RESP_0); in si_send_msg_to_smc()
188 tmp = RREG32(SMC_RESP_0); in si_send_msg_to_smc()
291 *value = RREG32(SMC_IND_DATA_0); in si_read_smc_sram_dword()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvce_v1_0.c78 return RREG32(mmVCE_RB_RPTR); in vce_v1_0_ring_get_rptr()
80 return RREG32(mmVCE_RB_RPTR2); in vce_v1_0_ring_get_rptr()
95 return RREG32(mmVCE_RB_WPTR); in vce_v1_0_ring_get_wptr()
97 return RREG32(mmVCE_RB_WPTR2); in vce_v1_0_ring_get_wptr()
123 if (RREG32(mmVCE_LMI_STATUS) & 0x337f) in vce_v1_0_lmi_clean()
139 if (RREG32(mmVCE_STATUS) & VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK) in vce_v1_0_firmware_loaded()
162 tmp = RREG32(mmVCE_CLOCK_GATING_A); in vce_v1_0_init_cg()
166 tmp = RREG32(mmVCE_CLOCK_GATING_B); in vce_v1_0_init_cg()
171 tmp = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v1_0_init_cg()
175 tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING); in vce_v1_0_init_cg()
[all …]
H A Damdgpu_i2c.c50 temp = RREG32(rec->mask_clk_reg); in amdgpu_i2c_pre_xfer()
56 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; in amdgpu_i2c_pre_xfer()
59 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; in amdgpu_i2c_pre_xfer()
63 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; in amdgpu_i2c_pre_xfer()
66 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; in amdgpu_i2c_pre_xfer()
70 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; in amdgpu_i2c_pre_xfer()
72 temp = RREG32(rec->mask_clk_reg); in amdgpu_i2c_pre_xfer()
74 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; in amdgpu_i2c_pre_xfer()
76 temp = RREG32(rec->mask_data_reg); in amdgpu_i2c_pre_xfer()
89 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; in amdgpu_i2c_post_xfer()
[all …]
H A Dvce_v2_0.c65 return RREG32(mmVCE_RB_RPTR); in vce_v2_0_ring_get_rptr()
67 return RREG32(mmVCE_RB_RPTR2); in vce_v2_0_ring_get_rptr()
82 return RREG32(mmVCE_RB_WPTR); in vce_v2_0_ring_get_wptr()
84 return RREG32(mmVCE_RB_WPTR2); in vce_v2_0_ring_get_wptr()
110 uint32_t status = RREG32(mmVCE_LMI_STATUS); in vce_v2_0_lmi_clean()
127 uint32_t status = RREG32(mmVCE_STATUS); in vce_v2_0_firmware_loaded()
156 tmp = RREG32(mmVCE_CLOCK_GATING_A); in vce_v2_0_init_cg()
162 tmp = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v2_0_init_cg()
167 tmp = RREG32(mmVCE_CLOCK_GATING_B); in vce_v2_0_init_cg()
213 return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK); in vce_v2_0_is_idle()
[all …]
H A Diceland_ih.c62 u32 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_enable_interrupts()
63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in iceland_ih_enable_interrupts()
81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in iceland_ih_disable_interrupts()
82 u32 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_disable_interrupts()
117 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); in iceland_ih_irq_init()
148 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_irq_init()
207 wptr = RREG32(mmIH_RB_WPTR); in iceland_ih_get_wptr()
220 tmp = RREG32(mmIH_RB_CNTL); in iceland_ih_get_wptr()
351 u32 tmp = RREG32(mmSRBM_STATUS); in iceland_ih_is_idle()
367 tmp = RREG32(mmSRBM_STATUS); in iceland_ih_wait_for_idle()
[all …]
H A Dcz_ih.c62 u32 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_enable_interrupts()
63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cz_ih_enable_interrupts()
81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cz_ih_disable_interrupts()
82 u32 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_disable_interrupts()
117 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); in cz_ih_irq_init()
148 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_irq_init()
207 wptr = RREG32(mmIH_RB_WPTR); in cz_ih_get_wptr()
221 tmp = RREG32(mmIH_RB_CNTL); in cz_ih_get_wptr()
357 u32 tmp = RREG32(mmSRBM_STATUS); in cz_ih_is_idle()
373 tmp = RREG32(mmSRBM_STATUS); in cz_ih_wait_for_idle()
[all …]
H A Duvd_v3_1.c48 return RREG32(mmUVD_RBC_RB_RPTR); in uvd_v3_1_ring_get_rptr()
62 return RREG32(mmUVD_RBC_RB_WPTR); in uvd_v3_1_ring_get_wptr()
155 tmp = RREG32(mmUVD_CONTEXT_ID); in uvd_v3_1_ring_test_ring()
213 tmp = RREG32(mmUVD_CGC_CTRL); in uvd_v3_1_set_dcm()
246 if (RREG32(mmUVD_FW_START)) in uvd_v3_1_mc_resume()
291 if (RREG32(mmUVD_FW_START) & UVD_FW_STATUS__PASS_MASK) { in uvd_v3_1_fw_validate()
293 RREG32(mmUVD_FW_START), adev->uvd.keyselect); in uvd_v3_1_fw_validate()
301 if (RREG32(mmUVD_FW_STATUS) & UVD_FW_STATUS__DONE_MASK) in uvd_v3_1_fw_validate()
308 if (!(RREG32(mmUVD_FW_STATUS) & UVD_FW_STATUS__PASS_MASK)) in uvd_v3_1_fw_validate()
313 if (!(RREG32(mmUVD_FW_STATUS) & UVD_FW_STATUS__BUSY_MASK)) in uvd_v3_1_fw_validate()
[all …]
H A Dcik_ih.c62 u32 ih_cntl = RREG32(mmIH_CNTL); in cik_ih_enable_interrupts()
63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cik_ih_enable_interrupts()
81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cik_ih_disable_interrupts()
82 u32 ih_cntl = RREG32(mmIH_CNTL); in cik_ih_disable_interrupts()
117 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); in cik_ih_irq_init()
210 tmp = RREG32(mmIH_RB_CNTL); in cik_ih_get_wptr()
363 u32 tmp = RREG32(mmSRBM_STATUS); in cik_ih_is_idle()
379 tmp = RREG32(mmSRBM_STATUS) & SRBM_STATUS__IH_BUSY_MASK; in cik_ih_wait_for_idle()
392 u32 tmp = RREG32(mmSRBM_STATUS); in cik_ih_soft_reset()
398 tmp = RREG32(mmSRBM_SOFT_RESET); in cik_ih_soft_reset()
[all …]
H A Dsi_ih.c38 u32 ih_cntl = RREG32(IH_CNTL); in si_ih_enable_interrupts()
39 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_ih_enable_interrupts()
50 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_ih_disable_interrupts()
51 u32 ih_cntl = RREG32(IH_CNTL); in si_ih_disable_interrupts()
72 interrupt_cntl = RREG32(INTERRUPT_CNTL); in si_ih_irq_init()
126 tmp = RREG32(IH_RB_CNTL); in si_ih_get_wptr()
229 u32 tmp = RREG32(mmSRBM_STATUS); in si_ih_is_idle()
255 u32 tmp = RREG32(mmSRBM_STATUS); in si_ih_soft_reset()
261 tmp = RREG32(mmSRBM_SOFT_RESET); in si_ih_soft_reset()
265 tmp = RREG32(mmSRBM_SOFT_RESET); in si_ih_soft_reset()
[all …]
H A Damdgpu_amdkfd_gfx_v7.c107 while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid))) in kgd_set_pasid_vmid_mapping()
214 (*dump)[i++][1] = RREG32(addr); \ in kgd_hqd_dump()
255 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); in kgd_hqd_sdma_load()
329 act = RREG32(mmCP_HQD_ACTIVE); in kgd_hqd_is_occupied()
334 if (low == RREG32(mmCP_HQD_PQ_BASE) && in kgd_hqd_is_occupied()
335 high == RREG32(mmCP_HQD_PQ_BASE_HI)) in kgd_hqd_is_occupied()
351 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL); in kgd_hqd_sdma_is_occupied()
397 temp = RREG32(mmCP_HQD_IQ_TIMER); in kgd_hqd_destroy()
426 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); in kgd_hqd_destroy()
445 temp = RREG32(mmCP_HQD_ACTIVE); in kgd_hqd_destroy()
[all …]
H A Dvce_v3_0.c90 v = RREG32(mmVCE_RB_RPTR); in vce_v3_0_ring_get_rptr()
92 v = RREG32(mmVCE_RB_RPTR2); in vce_v3_0_ring_get_rptr()
94 v = RREG32(mmVCE_RB_RPTR3); in vce_v3_0_ring_get_rptr()
122 v = RREG32(mmVCE_RB_WPTR); in vce_v3_0_ring_get_wptr()
124 v = RREG32(mmVCE_RB_WPTR2); in vce_v3_0_ring_get_wptr()
126 v = RREG32(mmVCE_RB_WPTR3); in vce_v3_0_ring_get_wptr()
182 data = RREG32(mmVCE_CLOCK_GATING_B); in vce_v3_0_set_vce_sw_clock_gating()
187 data = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v3_0_set_vce_sw_clock_gating()
192 data = RREG32(mmVCE_UENC_CLOCK_GATING_2); in vce_v3_0_set_vce_sw_clock_gating()
197 data = RREG32(mmVCE_UENC_REG_CLOCK_GATING); in vce_v3_0_set_vce_sw_clock_gating()
[all …]
H A Damdgpu_amdkfd_gfx_v8.c102 while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid))) in kgd_set_pasid_vmid_mapping()
177 value = RREG32(mmRLC_CP_SCHEDULERS); in kgd_hqd_load()
238 (*dump)[i++][1] = RREG32(addr); \ in kgd_hqd_dump()
278 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); in kgd_hqd_sdma_load()
361 act = RREG32(mmCP_HQD_ACTIVE); in kgd_hqd_is_occupied()
366 if (low == RREG32(mmCP_HQD_PQ_BASE) && in kgd_hqd_is_occupied()
367 high == RREG32(mmCP_HQD_PQ_BASE_HI)) in kgd_hqd_is_occupied()
383 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL); in kgd_hqd_sdma_is_occupied()
432 temp = RREG32(mmCP_HQD_IQ_TIMER); in kgd_hqd_destroy()
461 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); in kgd_hqd_destroy()
[all …]
H A Dvpe_v6_1.c79 f32_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_F32_CNTL)); in vpe_v6_1_halt()
109 vpe_colla_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_COLLABORATE_CNTL)); in vpe_v6_1_set_collaborate_mode()
114 vpe_colla_cfg = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_COLLABORATE_CFG)); in vpe_v6_1_set_collaborate_mode()
136 ret = RREG32(vpe_get_reg_offset(vpe, j, regVPEC_CNTL_6_1_1)); in vpe_v6_1_load_microcode()
138 ret = RREG32(vpe_get_reg_offset(vpe, j, regVPEC_CNTL)); in vpe_v6_1_load_microcode()
162 f32_cntl = RREG32(f32_offset); in vpe_v6_1_load_microcode()
218 rb_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL)); in vpe_v6_1_ring_start()
250 doorbell_offset = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL_OFFSET)); in vpe_v6_1_ring_start()
254 doorbell = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL)); in vpe_v6_1_ring_start()
264 ib_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_IB_CNTL)); in vpe_v6_1_ring_start()
[all …]

12345