Lines Matching refs:RREG32
81 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) in r100_is_in_vblank()
86 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) in r100_is_in_vblank()
98 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
99 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
101 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
102 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
126 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN)) in r100_wait_for_vblank()
129 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN)) in r100_wait_for_vblank()
185 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) in r100_page_flip()
211 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & in r100_page_flip_pending()
371 tmp = RREG32(voltage->gpio.reg); in r100_pm_misc()
380 tmp = RREG32(voltage->gpio.reg); in r100_pm_misc()
472 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); in r100_pm_prepare()
476 tmp = RREG32(RADEON_CRTC_GEN_CNTL); in r100_pm_prepare()
503 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); in r100_pm_finish()
507 tmp = RREG32(RADEON_CRTC_GEN_CNTL); in r100_pm_finish()
525 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) in r100_gui_idle()
547 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) in r100_hpd_sense()
551 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) in r100_hpd_sense()
576 tmp = RREG32(RADEON_FP_GEN_CNTL); in r100_hpd_set_polarity()
584 tmp = RREG32(RADEON_FP2_GEN_CNTL); in r100_hpd_set_polarity()
676 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; in r100_pci_gart_enable()
683 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; in r100_pci_gart_enable()
698 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; in r100_pci_gart_disable()
752 RREG32(RADEON_GEN_INT_CNTL); in r100_irq_set()
764 tmp = RREG32(R_000044_GEN_INT_STATUS); in r100_irq_disable()
770 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); in r100_irq_ack()
833 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; in r100_irq_process()
848 return RREG32(RADEON_CRTC_CRNT_FRAME); in r100_get_vblank_counter()
850 return RREG32(RADEON_CRTC2_CRNT_FRAME); in r100_get_vblank_counter()
984 tmp = RREG32(R_000E40_RBBM_STATUS); in r100_cp_wait_for_idle()
1101 rptr = RREG32(RADEON_CP_RB_RPTR); in r100_gfx_get_rptr()
1109 return RREG32(RADEON_CP_RB_WPTR); in r100_gfx_get_wptr()
1116 (void)RREG32(RADEON_CP_RB_WPTR); in r100_gfx_set_wptr()
2504 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; in r100_rbbm_fifo_wait_for_entry()
2522 tmp = RREG32(RADEON_RBBM_STATUS); in r100_gui_wait_for_idle()
2538 tmp = RREG32(RADEON_MC_STATUS); in r100_mc_wait_for_idle()
2551 rbbm_status = RREG32(R_000E40_RBBM_STATUS); in r100_gpu_is_lockup()
2564 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; in r100_enable_bm()
2573 tmp = RREG32(R_000030_BUS_CNTL); in r100_bm_disable()
2579 tmp = RREG32(RADEON_BUS_CNTL); in r100_bm_disable()
2591 status = RREG32(R_000E40_RBBM_STATUS); in r100_asic_reset()
2596 status = RREG32(R_000E40_RBBM_STATUS); in r100_asic_reset()
2600 tmp = RREG32(RADEON_CP_RB_CNTL); in r100_asic_reset()
2613 RREG32(R_0000F0_RBBM_SOFT_RESET); in r100_asic_reset()
2617 status = RREG32(R_000E40_RBBM_STATUS); in r100_asic_reset()
2621 RREG32(R_0000F0_RBBM_SOFT_RESET); in r100_asic_reset()
2625 status = RREG32(R_000E40_RBBM_STATUS); in r100_asic_reset()
2686 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); in r100_set_common_regs()
2687 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); in r100_set_common_regs()
2688 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); in r100_set_common_regs()
2734 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) in r100_vram_get_type()
2739 tmp = RREG32(RADEON_MEM_CNTL); in r100_vram_get_type()
2750 tmp = RREG32(RADEON_MEM_CNTL); in r100_vram_get_type()
2767 aper_size = RREG32(RADEON_CONFIG_APER_SIZE); in r100_get_accessible_vram()
2795 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) in r100_get_accessible_vram()
2811 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); in r100_vram_init_sizes()
2815 tom = RREG32(RADEON_NB_TOM); in r100_vram_init_sizes()
2820 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); in r100_vram_init_sizes()
2845 temp = RREG32(RADEON_CONFIG_CNTL); in r100_vga_set_state()
2863 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; in r100_mc_init()
2878 (void)RREG32(RADEON_CLOCK_CNTL_DATA); in r100_pll_errata_after_index()
2879 (void)RREG32(RADEON_CRTC_GEN_CNTL); in r100_pll_errata_after_index()
2900 save = RREG32(RADEON_CLOCK_CNTL_INDEX); in r100_pll_errata_after_data()
2903 tmp = RREG32(RADEON_CLOCK_CNTL_DATA); in r100_pll_errata_after_data()
2916 data = RREG32(RADEON_CLOCK_CNTL_DATA); in r100_pll_rreg()
2957 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); in r100_debugfs_rbbm_info_show()
2958 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); in r100_debugfs_rbbm_info_show()
2959 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); in r100_debugfs_rbbm_info_show()
2962 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; in r100_debugfs_rbbm_info_show()
2964 value = RREG32(RADEON_RBBM_CMDFIFO_DATA); in r100_debugfs_rbbm_info_show()
2978 rdp = RREG32(RADEON_CP_RB_RPTR); in r100_debugfs_cp_ring_info_show()
2979 wdp = RREG32(RADEON_CP_RB_WPTR); in r100_debugfs_cp_ring_info_show()
2981 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); in r100_debugfs_cp_ring_info_show()
3003 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); in r100_debugfs_cp_csq_fifo_show()
3004 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); in r100_debugfs_cp_csq_fifo_show()
3005 csq_stat = RREG32(RADEON_CP_CSQ_STAT); in r100_debugfs_cp_csq_fifo_show()
3006 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); in r100_debugfs_cp_csq_fifo_show()
3026 tmp = RREG32(RADEON_CP_CSQ_DATA); in r100_debugfs_cp_csq_fifo_show()
3032 tmp = RREG32(RADEON_CP_CSQ_DATA); in r100_debugfs_cp_csq_fifo_show()
3038 tmp = RREG32(RADEON_CP_CSQ_DATA); in r100_debugfs_cp_csq_fifo_show()
3049 tmp = RREG32(RADEON_CONFIG_MEMSIZE); in r100_debugfs_mc_info_show()
3051 tmp = RREG32(RADEON_MC_FB_LOCATION); in r100_debugfs_mc_info_show()
3053 tmp = RREG32(RADEON_BUS_CNTL); in r100_debugfs_mc_info_show()
3055 tmp = RREG32(RADEON_MC_AGP_LOCATION); in r100_debugfs_mc_info_show()
3057 tmp = RREG32(RADEON_AGP_BASE); in r100_debugfs_mc_info_show()
3059 tmp = RREG32(RADEON_HOST_PATH_CNTL); in r100_debugfs_mc_info_show()
3061 tmp = RREG32(0x01D0); in r100_debugfs_mc_info_show()
3063 tmp = RREG32(RADEON_AIC_LO_ADDR); in r100_debugfs_mc_info_show()
3065 tmp = RREG32(RADEON_AIC_HI_ADDR); in r100_debugfs_mc_info_show()
3067 tmp = RREG32(0x01E4); in r100_debugfs_mc_info_show()
3265 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); in r100_bandwidth_update()
3311 temp = RREG32(RADEON_MEM_TIMING_CNTL); in r100_bandwidth_update()
3351 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); in r100_bandwidth_update()
3372 temp = RREG32(RADEON_MEM_CNTL); in r100_bandwidth_update()
3376 temp = RREG32(R300_MC_IND_INDEX); in r100_bandwidth_update()
3380 temp = RREG32(R300_MC_IND_DATA); in r100_bandwidth_update()
3383 temp = RREG32(R300_MC_READ_CNTL_AB); in r100_bandwidth_update()
3387 temp = RREG32(R300_MC_READ_CNTL_AB); in r100_bandwidth_update()
3523 temp = RREG32(RADEON_GRPH_BUFFER_CNTL); in r100_bandwidth_update()
3546 temp = RREG32(RS400_DISP1_REG_CNTL); in r100_bandwidth_update()
3552 temp = RREG32(RS400_DMIF_MEM_CNTL1); in r100_bandwidth_update()
3563 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); in r100_bandwidth_update()
3579 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); in r100_bandwidth_update()
3638 temp = RREG32(RS400_DISP2_REQ_CNTL1); in r100_bandwidth_update()
3644 temp = RREG32(RS400_DISP2_REQ_CNTL2); in r100_bandwidth_update()
3658 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); in r100_bandwidth_update()
3692 tmp = RREG32(scratch); in r100_ring_test()
3769 tmp = RREG32(scratch); in r100_ib_test()
3799 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); in r100_mc_stop()
3800 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); in r100_mc_stop()
3801 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); in r100_mc_stop()
3803 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); in r100_mc_stop()
3804 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); in r100_mc_stop()
3817 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); in r100_mc_stop()
3937 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in r100_startup()
3966 RREG32(R_000E40_RBBM_STATUS), in r100_resume()
3967 RREG32(R_0007C0_CP_STAT)); in r100_resume()
4024 tmp = RREG32(RADEON_CP_CSQ_CNTL); in r100_restore_sanity()
4028 tmp = RREG32(RADEON_CP_RB_CNTL); in r100_restore_sanity()
4032 tmp = RREG32(RADEON_SCRATCH_UMSK); in r100_restore_sanity()
4070 RREG32(R_000E40_RBBM_STATUS), in r100_init()
4071 RREG32(R_0007C0_CP_STAT)); in r100_init()