78 		return RREG32(mmVCE_RB_RPTR);  in vce_v1_0_ring_get_rptr()
80 		return RREG32(mmVCE_RB_RPTR2);  in vce_v1_0_ring_get_rptr()
95 		return RREG32(mmVCE_RB_WPTR);  in vce_v1_0_ring_get_wptr()
97 		return RREG32(mmVCE_RB_WPTR2);  in vce_v1_0_ring_get_wptr()
123 			if (RREG32(mmVCE_LMI_STATUS) & 0x337f)  in vce_v1_0_lmi_clean()
139 			if (RREG32(mmVCE_STATUS) & VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK)  in vce_v1_0_firmware_loaded()
162 	tmp = RREG32(mmVCE_CLOCK_GATING_A);  in vce_v1_0_init_cg()
166 	tmp = RREG32(mmVCE_CLOCK_GATING_B);  in vce_v1_0_init_cg()
171 	tmp = RREG32(mmVCE_UENC_CLOCK_GATING);  in vce_v1_0_init_cg()
175 	tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);  in vce_v1_0_init_cg()
261 		if (RREG32(mmVCE_FW_REG_STATUS) & VCE_FW_REG_STATUS__DONE_MASK)  in vce_v1_0_wait_for_fw_validation()
265 	if (!(RREG32(mmVCE_FW_REG_STATUS) & VCE_FW_REG_STATUS__DONE_MASK)) {  in vce_v1_0_wait_for_fw_validation()
270 	if (!(RREG32(mmVCE_FW_REG_STATUS) & VCE_FW_REG_STATUS__PASS_MASK)) {  in vce_v1_0_wait_for_fw_validation()
277 		if (!(RREG32(mmVCE_FW_REG_STATUS) & VCE_FW_REG_STATUS__BUSY_MASK))  in vce_v1_0_wait_for_fw_validation()
281 	if (RREG32(mmVCE_FW_REG_STATUS) & VCE_FW_REG_STATUS__BUSY_MASK) {  in vce_v1_0_wait_for_fw_validation()
298 	if (RREG32(mmVCE_LMI_FW_START_KEYSEL)) {  in vce_v1_0_mc_resume()
300 			RREG32(mmVCE_LMI_FW_START_KEYSEL), adev->vce.keyselect);  in vce_v1_0_mc_resume()
361 		(RREG32(mmVCE_STATUS) & (VCE_STATUS__JOB_BUSY_MASK | VCE_STATUS__UENC_BUSY_MASK)) ||  in vce_v1_0_is_idle()
362 		(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);  in vce_v1_0_is_idle()
455 			RREG32(mmVCE_STATUS), RREG32(mmSRBM_STATUS2));  in vce_v1_0_stop()
461 		status = RREG32(mmVCE_LMI_STATUS);  in vce_v1_0_stop()
485 		tmp = RREG32(mmVCE_CLOCK_GATING_A);  in vce_v1_0_enable_mgcg()
489 		tmp = RREG32(mmVCE_UENC_CLOCK_GATING);  in vce_v1_0_enable_mgcg()
494 		tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);  in vce_v1_0_enable_mgcg()
498 		tmp = RREG32(mmVCE_CLOCK_GATING_A);  in vce_v1_0_enable_mgcg()
502 		tmp = RREG32(mmVCE_UENC_CLOCK_GATING);  in vce_v1_0_enable_mgcg()
507 		tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);  in vce_v1_0_enable_mgcg()